Low-power logic circuit and SRAM cell applications with silicon on depletion Layer CMOS (SODEL CMOS) technology. - Satoshi Inaba; Hajime Nagano; Kiyotaka Miyano; Ichiro Mizushima; Yasunori Okayama; Takahiro Nakauchi; Kazunari Ishimaru; Hidemi Ishiuchi (IEEE J. Solid State Circuits, 2006)

45nm/32nm CMOS ˜ Challenge and Perspective ˜. - Kazunari Ishimaru (ESSCIRC, 2007)

Challenges of Flash Memory for Next Decade. - Kazunari Ishimaru (IRPS, 2021)