A new horizontal and vertical common subexpression elimination method for multiple constant multiplication. - Kazunari Kato; Yasuhiro Takahashi; Toshikazu Sekine (ICECS, 2009)

Skew tolerance analysis and layout design of 4×4 multiplier using two phase clocking subthreshold adiabatic logic. - Kazunari Kato; Yasuhiro Takahashi; Toshikazu Sekine (APCCAS, 2014)

Two phase clocking subthreshold adiabatic logic. - Kazunari Kato; Yasuhiro Takahashi; Toshikazu Sekine (ISCAS, 2014)

A 4×4-bit multiplier LSI implementation of two phase clocking subthreshold adiabatic logic. - Kazunari Kato; Yasuhiro Takahashi; Toshikazu Sekine (NEWCAS, 2015)

Two phase clocked subthreshold adiabatic logic circuit. - Kazunari Kato; Yasuhiro Takahashi; Toshikazu Sekine (IEICE Electron. Express, 2015)