Enhancing Random-Pattern Coverage of Programmable Logic Arrays via Masking Technique. - Hideo Fujiwara; Osamu Fujisawa; Kazunori Hikone (ITC, 1988)

Sequential Test Generation Based on Real-Value Logic. - Kazumi Hatayama; Kazunori Hikone; Mitsuji Ikeda; Terumine Hayashi (ITC, 1992)

Sequential circuit test generation by real number simulation. - Kazunori Hikone; Mitsuji Ikeda; Kazumi Hatayama; Terumine Hayashi (Syst. Comput. Jpn., 1993)

A practical approach to instruction-based test generation for functional modules of VLSI processors. - Kazumi Hatayama; Kazunori Hikone; Takeshi Miyazaki; Hiromichi Yamada (VTS, 1997)