An experimental 16-Mbit CMOS DRAM chip with a 100-MHz serial read/write mode. - Shigeyoshi Watanabe; Yukihito Oowaki; Yasuo Itoh; Koji Sakui; Kenji Numata; Tsuneaki Fuse; Takayuki Kobayashi; Kenji Tsuchida; Masahiko Chiba; Takahiko Hara; Masako Ohta; Fumio Horiguchi; et al. (IEEE J. Solid State Circuits, 1989)

New nibbled-page architecture for high-density DRAMs. - Kenji Numata; Yukihito Oowaki; Yasuo Itoh; Takahiko Hara; Kenji Tsuchida; Masako Ohta; Shigyoshi Watanabe; Kazunori Ohuchi (IEEE J. Solid State Circuits, 1989)

An experimental 4-Mbit CMOS EEPROM with a NAND-structured cell. - Masaki Momodomi; Yasuo Itoh; Riichiro Shirota; Yoshihisa Iwata; Ryozo Nakayama; Ryouhei Kirisawa; Tomoharu Tanaka; Seiichi Aritome; Tetsuo Endoh; Kazunori Ohuchi; Fujjo Masuoka (IEEE J. Solid State Circuits, 1989)

A high-density NAND EEPROM with block-page programming for microcomputer applications. - Yoshihisa Iwata; Masaki Momodomi; Tomoharu Tanaka; Hideko Oodaira; Yasuo Itoh; Ryozo Nakayama; Ryouhei Kirisawa; Seiichi Aritome; Tetsuo Endoh; Riichiro Shirota; Kazunori Ohuchi; Fujio Masuoka (IEEE J. Solid State Circuits, 1990)

A 4 Mb NAND EEPROM with tight programmed Vt distribution. - Masaki Momodomi; Tomoharu Tanaka; Yoshihisa Iwata; Yoshiyuki Tanaka; Hideko Oodaira; Yasuo Itoh; Riichiro Shirota; Kazunori Ohuchi; Fujio Masuoka (IEEE J. Solid State Circuits, 1991)

A 33-ns 64-Mb DRAM. - Yukihito Oowaki; Kenji Tsuchida; Yohji Watanabe; Daisaburo Takashima; Masako Ohta; Hiroaki Nakano; Shigeyoshi Watanabe; Akihiro Nitayama; Fumio Horiguchi; Kazunori Ohuchi; Fujio Masuoka (IEEE J. Solid State Circuits, 1991)

Word-line architecture for highly reliable 64-Mb DRAM. - Daisaburo Takashima; Yukihito Oowaki; Ryu Ogiwara; Yohji Watanabe; Kenji Tsuchida; Masako Ohta; Hiroaki Nakano; Shigeyoshi Watanabe; Kazunori Ohuchi (IEEE J. Solid State Circuits, 1992)

Open/folded bit-line arrangement for ultra-high-density DRAM's. - Daisaburo Takashima; Shigeyoshi Watanabe; Hiroaki Nakano; Yukihito Oowaki; Kazunori Ohuchi (IEEE J. Solid State Circuits, 1994)

Standby/active mode logic for sub-1-V operating ULSI memory. - Daisaburo Takashima; Shigeyoshi Watanabe; Hiroalu Nakano; Yukihito Oowaki; Kazunori Ohuchi; Hiroyuki Tango (IEEE J. Solid State Circuits, 1994)

A quick intelligent page-programming architecture and a shielded bitline sensing method for 3 V-only NAND flash memory. - Tomoharu Tanaka; Yoshiyuki Tanaka; Hiroshi Nakamura; Koji Sakui; Hideko Oodaira; Riichiro Shirota; Kazunori Ohuchi; Fujio Masuoka; Hisashi Hara (IEEE J. Solid State Circuits, 1994)

A compact on-chip ECC for low cost flash memories. - Toru Tanzawa; Tomoharu Tanaka; Ken Takeuchi; Riichiro Shirota; Seiichi Aritome; Hiroshi Watanabe; Gertjan Hemink; Kazuhiro Shimizu; Shinji Sato; Yuji Takeuchi; Kazunori Ohuchi (IEEE J. Solid State Circuits, 1997)

Noise suppression scheme for gigabit-scale and gigabyte/s data-rate LSI's. - Daisaburo Takashima; Yukihito Oowaki; Shigeyoshi Watanabe; Kazunori Ohuchi (IEEE J. Solid State Circuits, 1998)