Multimedia applications of microprocessor with embedded DRAM. - Yasuhiro Nunomura; Toru Shimizu; Kazunori Saitoh; Koji Tsuchihashi (ICASSP, 1998)

A 40GOPS 250mW massively parallel processor based on matrix architecture. - Masami Nakajima; Hideyuki Noda; Katsumi Dosaka; Kiyoshi Nakata; Motoki Higashida; Osamu Yamamoto; Katsuya Mizumoto; Hiroyuki Kondo; Yukihiko Shimazu; Kazutami Arimoto; Kazunori Saitoh; Toru Shimizu (ISSCC, 2006)