An experimental soft-error-immune 64-kbit 3-ns ECL bipolar RAM. - Kunihiko Yamaguchi; Hiroaki Nanbu; Kazuo Kanetani; Noriyuki Homma; Tohru Nakamura; Kenichi Ohhata; Akihisa Uchida; Katsumi Ogiue (IEEE J. Solid State Circuits, 1989)

A 1.5-ns access time, 78- mu m2 memory-cell size, 64-kb ECL-CMOS SRAM. - Kunihiko Yamaguchi; Hiroaki Nambu; Kazuo Kanetani; Youji Idei; Noriyuki Homma; Toshiro Hiramoto; Nobuo Tamba; Kunihiko Watanabe; Masanori Odaka; Takahide Ikeda; Kenichi Ohhata; Yoshiaki Sakurai (IEEE J. Solid State Circuits, 1992)

High-speed sensing techniques for ultrahigh-speed SRAMs. - Hiroaki Nambu; Kazuo Kanetani; Youji Idei; Noriyuki Homma; Kunihiko Yamaguchi; Toshiro Hiramoto; Nobuo Tamba; Masanori Odaka; Kunihiko Watanabe; Takahide Ikeda; Kenichi Ohhata; Yoshiaki Sakurai (IEEE J. Solid State Circuits, 1992)

A 0.65-ns, 72-kb ECL-CMOS RAM macro for a 1-Mb SRAM. - Hiroalu Nambu; Kazuo Kanetani; Youji Idei; Tom Masuda; Keiichi Higeta; Masayuki Ohayashi; Masami Usami; Kunihiko Yamaguchi; Toshiyuki Kikuchi; Takahide Ikeda; Kenichi Ohhata; Takeshi Kusunoki; et al. (IEEE J. Solid State Circuits, 1995)

A 1.8-ns access, 550-MHz, 4.5-Mb CMOS SRAM. - Hiroaki Nambu; Kazuo Kanetani; Kaname Yamasaki; Keiichi Higeta; Masami Usami; Yasuhiro Fujimura; Kazumasa Ando; Takeshi Kusunoki; Kunihiko Yamaguchi; Noriyuki Homma (IEEE J. Solid State Circuits, 1998)

A 550-ps access 900-MHz 1-Mb ECL-CMOS SRAM. - Hiroaki Nambu; Kazuo Kanetani; Kaname Yamasaki; Keiichi Higeta; Masami Usami; Masahiko Nishiyama; Kenichi Ohhata; Fumihiko Arakawa; Takeshi Kusunoki; Kunihiko Yamaguchi; Atsuo Hotta; Noriyuki Homma (IEEE J. Solid State Circuits, 2000)

Power reduction techniques for a 1-Mb ECL-CMOS SRAM with an access time of 550 ps and an operating frequency of 900 MHz. - Kenichi Ohhata; Fumihiko Arakawa; Takeshi Kusunoki; Hiroaki Nambu; Kazuo Kanetani; Kaname Yamasaki; Keiichi Higeta; Masami Usami; Masahiko Nishiyama; Kunihiko Yamaguchi; Noriyuki Homma; Atsuo Hotta (IEEE J. Solid State Circuits, 2000)