A charge-transfer amplifier and an encoded-bus architecture for low-power SRAM's. - Shoichiro Kawashima; Toshihiko Mori; Ryuhei Sasagawa; Makoto Hamaminato; Shigetoshi Wakayama; Kazuo Sukegawa; Isao Fukushi (IEEE J. Solid State Circuits, 1998)

A 0.11 mum CMOS technology featuring copper and very low k interconnects with high performance and reliability. - Yoshihiro Takao; Hiroshi Kudo; Junichi Mitani; Yoshiyuki Kotani; Satoshi Yamaguchi; Keizaburo Yoshie; Kazuo Sukegawa; Nobuhisa Naori; Satoru Asai; Michiari Kawano (Microelectron. Reliab., 2002)