A partial redundant fault-secure high-level synthesis algorithm for RDR architectures. - Kazushi Kawamura; Sho Tanaka; Masao Yanagisawa; Nozomu Togawa (ISCAS, 2013)

A Thermal-Aware High-Level Synthesis Algorithm for RDR Architectures through Binding and Allocation. - Kazushi Kawamura; Masao Yanagisawa; Nozomu Togawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013)

A floorplan-aware high-level synthesis algorithm for multiplexer reduction targeting FPGA designs. - Koichi Fujiwara; Shin-ya Abe; Kazushi Kawamura; Masao Yanagisawa; Nozomu Togawa (APCCAS, 2014)

An H∞ controller design based on the butterworth filter conversion. - Kazushi Kawamura; Hiroki Shibasaki; Rubiyah Yusof; Yoshihisa Ishida (ASCC, 2015)

Clock skew estimate modeling for FPGA high-level synthesis and its application. - Koichi Fujiwara; Kazushi Kawamura; Masao Yanagisawa; Nozomu Togawa (ASICON, 2015)

A Floorplan-Driven High-Level Synthesis Algorithm for Multiplexer Reduction Targeting FPGA Designs. - Koichi Fujiwara; Kazushi Kawamura; Shin-ya Abe; Masao Yanagisawa; Nozomu Togawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015)

A high-performance circuit design algorithm using data dependent approximation. - Kazushi Kawamura; Masao Yanagisawa; Nozomu Togawa (ISOCC, 2016)

Rotator-based multiplexer network synthesis for field-data extractors. - Koki Ito; Kazushi Kawamura; Yutaka Tamiya; Masao Yanagisawa; Nozomu Togawa (SoCC, 2016)

Interconnection-Delay and Clock-Skew Estimate Modelings for Floorplan-Driven High-Level Synthesis Targeting FPGA Designs. - Koichi Fujiwara; Kazushi Kawamura; Masao Yanagisawa; Nozomu Togawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016)

Bi-Partitioning Based Multiplexer Network for Field-Data Extractors. - Koki Ito; Kazushi Kawamura; Yutaka Tamiya; Masao Yanagisawa; Nozomu Togawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016)

A selector-based FFT processor and its FPGA implementation. - Yuya Hirai; Kazushi Kawamura; Masao Yanagisawa; Nozomu Togawa (ISOCC, 2017)

Efficient Multiplexer Networks for Field-Data Extractors and Their Evaluations. - Koki Ito; Kazushi Kawamura; Yutaka Tamiya; Masao Yanagisawa; Nozomu Togawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017)

A loop structure optimization targeting high-level synthesis of fast number theoretic transform. - Kazushi Kawamura; Masao Yanagisawa; Nozomu Togawa (ISQED, 2018)

Mapping Constrained Slot-Placement Problems to Ising Models and its Evaluations by an Ising Machine. - Sho Kanamaru; Kazushi Kawamura; Shu Tanaka; Yoshinori Tomita; Hidetoshi Matsuoka; Kaoru Kawamura; Nozomu Togawa (ICCE-Berlin, 2019)

Implementation of a ROS-Based Autonomous Vehicle on an FPGA Board. - Kento Hasegawa; Kazunari Takasaki; Makoto Nishizawa; Ryota Ishikawa; Kazushi Kawamura; Nozomu Togawa (FPT, 2019)

An FPGA Implementation Method based on Distributed-register Architectures. - Koichi Fujiwara; Kazushi Kawamura; Masao Yanagisawa; Nozomu Togawa (IPSJ Trans. Syst. LSI Des. Methodol., 2019)

FPGA-based Heterogeneous Solver for Three-Dimensional Routing. - Kento Hasegawa; Ryota Ishikawa; Makoto Nishizawa; Kazushi Kawamura; Masashi Tawada; Nozomu Togawa (ASP-DAC, 2020)

ExtraFerns: Fully Parallel Ensemble Learning Technique with Non-Greedy yet Minimal Memory Access Training. - Shungo Kumazawa; Kazushi Kawamura; Thiem Van Chu; Masato Motomura; Jaehoon Yu (CANDAR, 2020)

ProgressiveNN: Achieving Computational Scalability without Network Alteration by MSB-first Accumulative Computation. - Junnosuke Suzuki; Kota Ando; Kazutoshi Hirose; Kazushi Kawamura; Thiem Van Chu; Masato Motomura; Jaehoon Yu (CANDAR, 2020)

A High-Performance and Flexible FPGA Inference Accelerator for Decision Forests Based on Prior Feature Space Partitioning. - Thiem Van Chu; Ryuichi Kitajima; Kazushi Kawamura; Jaehoon Yu; Masato Motomura (FPT, 2021)

Edge Inference Engine for Deep & Random Sparse Neural Networks with 4-bit Cartesian-Product MAC Array and Pipelined Activation Aligner. - Kota Ando; Jaehoon Yu; Kazutoshi Hirose; Hiroki Nakahara; Kazushi Kawamura; Thiem Van Chu; Masato Motomura (HCS, 2021)

Solving Constrained Slot Placement Problems Using an Ising Machine and Its Evaluations. - Sho Kanamaru; Kazushi Kawamura; Shu Tanaka; Yoshinori Tomita; Nozomu Togawa (IEICE Trans. Inf. Syst., 2021)

ExtraFerns: Fully Parallel Ensemble Learning Technique with Random Projection and Non-Greedy yet Minimal Memory Access Training. - Shungo Kumazawa; Kazushi Kawamura; Thiem Van Chu; Masato Motomura; Jaehoon Yu (Int. J. Netw. Comput., 2021)

ProgressiveNN: Achieving Computational Scalability with Dynamic Bit-Precision Adjustment by MSB-first Accumulative Computation. - Junnosuke Suzuki; Tomohiro Kaneko; Kota Ando; Kazutoshi Hirose; Kazushi Kawamura; Thiem Van Chu; Masato Motomura; Jaehoon Yu (Int. J. Netw. Comput., 2021)

STATICA: A 512-Spin 0.25M-Weight Annealing Processor With an All-Spin-Updates-at-Once Architecture for Combinatorial Optimization With Complete Spin-Spin Interactions. - Kasho Yamamoto; Kazushi Kawamura; Kota Ando; Normann Mertig; Takashi Takemoto; Masanao Yamaoka; Hiroshi Teramoto; Akira Sakai; Shinya Takamaeda-Yamazaki; Masato Motomura (IEEE J. Solid State Circuits, 2021)

Multicoated Supermasks Enhance Hidden Networks. - Yasuyuki Okoshi; Ángel López García-Arias; Kazutoshi Hirose; Kota Ando; Kazushi Kawamura; Thiem Van Chu; Masato Motomura; Jaehoon Yu (ICML, 2022)

APC-SCA: A Fully-Parallel Annealing Algorithm with Autonomous Pinning Effect Control. - Daiki Okonogi; Satoru Jimbo; Kota Ando; Thiem Van Chu; Jaehoon Yu; Masato Motomura; Kazushi Kawamura (IPDPS Workshops, 2022)

Hiddenite: 4K-PE Hidden Network Inference 4D-Tensor Engine Exploiting On-Chip Model Construction Achieving 34.8-to-16.0TOPS/W for CIFAR-100 and ImageNet. - Kazutoshi Hirose; Jaehoon Yu; Kota Ando; Yasuyuki Okoshi; Ángel López García-Arias; Junnosuke Suzuki; Thiem Van Chu; Kazushi Kawamura; Masato Motomura (ISSCC, 2022)

A Hybrid Integer Encoding Method for Obtaining High-Quality Solutions of Quadratic Knapsack Problems on Solid-State Annealers. - Satoru Jimbo; Daiki Okonogi; Kota Ando; Thiem Van Chu; Jaehoon Yu; Masato Motomura; Kazushi Kawamura (IEICE Trans. Inf. Syst., 2022)

Flexibly Controllable Dynamic Cooling Methods for Solid-State Annealing Processors to Improve Combinatorial Optimization Performance. - Genta Inoue; Daiki Okonogi; Thiem Van Chu; Jaehoon Yu; Masato Motomura; Kazushi Kawamura (COOL CHIPS, 2023)

Decision Forest Training Accelerator Based on Binary Feature Decomposition. - Thiem Van Chu; Yu Mizutani; Yuta Nagahara; Shungo Kumazawa; Kazushi Kawamura; Jaehoon Yu; Masato Motomura (FCCM, 2023)

Amorphica: 4-Replica 512 Fully Connected Spin 336MHz Metamorphic Annealer with Programmable Optimization Strategy and Compressed-Spin-Transfer Multi-Chip Extension. - Kazushi Kawamura; Jaehoon Yu; Daiki Okonogi; Satoru Jimbo; Genta Inoue; Akira Hyodo; Ángel López García-Arias; Kota Ando; Bruno Hideki Fukushima-Kimura; Ryota Yasudo; Thiem Van Chu; Masato Motomura (ISSCC, 2023)

Multicoated and Folded Graph Neural Networks With Strong Lottery Tickets. - Jiale Yan; Hiroaki Ito; Ángel López García-Arias; Yasuyuki Okoshi; Hikari Otsuka; Kazushi Kawamura; Thiem Van Chu; Masato Motomura (LoG, 2023)

A Highly Accurate and Parallel Vision MLP FPGA Accelerator based on FP7/8 SIMD Operations. - Mari Yasunaga; Junnosuke Suzuki; Masato Watanabe; Kazushi Kawamura; Thiem Van Chu; Jaehoon Yu; Masato Motomura (MCSoC, 2023)

Pianissimo: A Sub-mW Class DNN Accelerator with Progressive Bit-by-Bit Datapath Architecture for Adaptive Inference at Edge. - Junnosuke Suzuki; Jaehoon Yu; Mari Yasunaga; Ángel López García-Arias; Yasuyuki Okoshi; Shungo Kumazawa; Kota Ando; Kazushi Kawamura; Thiem Van Chu; Masato Motomura (VLSI Technology and Circuits, 2023)

A Fully-Parallel Annealing Algorithm with Autonomous Pinning Effect Control for Various Combinatorial Optimization Problems. - Daiki Okonogi; Satoru Jimbo; Kota Ando; Thiem Van Chu; Jaehoon Yu; Masato Motomura; Kazushi Kawamura (IEICE Trans. Inf. Syst., 2023)

Progressive Variable Precision DNN With Bitwise Ternary Accumulation. - Junnosuke Suzuki; Mari Yasunaga; Kazushi Kawamura; Thiem Van Chu; Masato Motomura (AICAS, 2024)

Sparse-Sparse Matrix Multiplication Accelerator on FPGA featuring Distribute-Merge Product Dataflow. - Yuta Nagahara; Jiale Yan; Kazushi Kawamura; Masato Motomura; Thiem Van Chu (ASPDAC, 2024)

WhiteDwarf: 12.24 TFLOPS/W 40 nm Versatile Neural Inference Engine for Ultra-Compact Execution of CNNs and MLPs Through Triple Unstructured Sparsity Exploitation and Triple Model Compression. - Yasuyuki Okoshi; Ángel López García-Arias; Jaehoon Yu; Junnosuke Suzuki; Hikari Otsuka; Thiem Van Chu; Kazushi Kawamura; Daichi Fujiki; Masato Motomura (A-SSCC, 2024)

Exploiting N:M Sparsity in Quantized-Folded ResNets: Signed Multicoat Supermasks and Iterative Pruning-Quantization. - Akihiro Shioda; Ángel López García-Arias; Hikari Otsuka; Yuki Ichikawa; Yasuyuki Okoshi; Kazushi Kawamura; Thiem Van Chu; Daichi Fujiki; Masato Motomura (CANDAR, 2024)

A Parallel-Trial Double-Update Annealing Processor for Enabling Highly-Effective Solution Search of Constrained Combinatorial Optimization Problems. - Akira Hyodo; Satoru Jimbo; Daiki Okonogi; Genta Inoue; Thiem Van Chu; Masato Motomura; Kazushi Kawamura (ICFPT, 2024)

Classical Thermodynamics-based Parallel Annealing Algorithm for High-speed and Robust Combinatorial Optimization. - Kyo Kuroki; Satoru Jimbo; Thiem Van Chu; Masato Motomura; Kazushi Kawamura (GECCO, 2024)

An Accurate FPGA-Based ORB Feature Extractor for SLAM with Row-Wise Keypoint Selection. - Yuki Ichikawa; Akihiro Shioda; Kazushi Kawamura; Thiem Van Chu; Masato Motomura (ICCE, 2024)

Efficient COO to CSR Conversion for Accelerating Sparse Matrix Processing on FPGA. - Yuta Nagahara; Jiale Yan; Kazushi Kawamura; Masato Motomura; Thiem Van Chu (ICCE, 2024)

Exploration of Hyperdimensional Computing Using Locality-Sensitive Hashing Mechanism on FPGA. - Masato Watanabe; Shungo Kumazawa; Thiem Van Chu; Kazushi Kawamura; Jaehoon Yu; Masato Motomura (ICCE, 2024)

High Throughput Datapath Design for Vision Permutator FPGA Accelerator. - Mari Yasunaga; Junnosuke Suzuki; Masato Watanabe; Kazushi Kawamura; Thiem Van Chu; Masato Motomura (ICCE, 2024)

ETreeNet: Ensemble Model Fusing Decision Trees and Neural Networks for Small Tabular Data. - Tsukasa Yamakura; Kazushi Kawamura; Masato Motomura; Thiem Van Chu (IJCNN, 2024)

Efficient Stereo Visual Odometry on FPGA Featuring On-Chip Map Management and Pipelined Descriptor-Based Block Matching. - Yuki Ichikawa; Kazushi Kawamura; Masato Motomura; Thiem Van Chu (IEEE Access, 2024)

A GPU-Based Ising Machine With a Multi-Spin-Flip Capability for Constrained Combinatorial Optimization. - Satoru Jimbo; Tatsuhiko Shirai; Nozomu Togawa; Masato Motomura; Kazushi Kawamura (IEEE Access, 2024)

Toward Improving Ensemble-Based Collaborative Inference at the Edge. - Shungo Kumazawa; Jaehoon Yu; Kazushi Kawamura; Thiem Van Chu; Masato Motomura (IEEE Access, 2024)

Pianissimo: A Sub-mW Class DNN Accelerator With Progressively Adjustable Bit-Precision. - Junnosuke Suzuki; Jaehoon Yu; Mari Yasunaga; Ángel López García-Arias; Yasuyuki Okoshi; Shungo Kumazawa; Kota Ando; Kazushi Kawamura; Thiem Van Chu; Masato Motomura (IEEE Access, 2024)

Partial Search in a Frozen Network is Enough to Find a Strong Lottery Ticket. - Hikari Otsuka; Daiki Chijiwa; Ángel López García-Arias; Yasuyuki Okoshi; Kazushi Kawamura; Thiem Van Chu; Daichi Fujiki; Susumu Takeuchi; Masato Motomura (CoRR, 2024)

Restricted Random Pruning at Initialization for High Compression Range. - Hikari Otsuka; Yasuyuki Okoshi; Ángel López García-Arias; Kazushi Kawamura; Thiem Van Chu; Daichi Fujiki; Masato Motomura (Trans. Mach. Learn. Res., 2024)

TTF-GNN: Memory-Efficient GNNs via Tensor Train Decomposition and Network Folding. - Hiroaki Ito; Jiale Yan; Kazushi Kawamura; Masato Motomura; Thiem Van Chu; Daichi Fujiki (COOL CHIPS, 2025)

BingoGCN: Towards Scalable and Efficient GNN Acceleration with Fine-Grained Partitioning and SLT. - Jiale Yan; Hiroaki Ito; Yuta Nagahara; Kazushi Kawamura; Masato Motomura; Thiem Van Chu; Daichi Fujiki (ISCA, 2025)

WhiteDwarf: A Holistic Co-Design Approach to Ultra-Compact Neural Inference Acceleration. - Ángel López García-Arias; Yasuyuki Okoshi; Jaehoon Yu; Junnosuke Suzuki; Hikari Otsuka; Kazushi Kawamura; Thiem Van Chu; Daichi Fujiki; Masato Motomura (IEEE Access, 2025)

A Flip-Count-Based Dynamic Temperature Control Method for Constrained Combinatorial Optimization by Parallel Annealing Algorithms. - Genta Inoue; Daiki Okonogi; Satoru Jimbo; Thiem Van Chu; Masato Motomura; Kazushi Kawamura (IEICE Trans. Inf. Syst., 2025)

Uncovering Strong Lottery Tickets in Graph Transformers: A Path to Memory Efficient and Robust Graph Learning. - Hiroaki Ito; Jiale Yan; Hikari Otsuka; Kazushi Kawamura; Masato Motomura; Thiem Van Chu; Daichi Fujiki (Trans. Mach. Learn. Res., 2025)

Partially Frozen Random Networks Contain Compact Strong Lottery Tickets. - Hikari Otsuka; Daiki Chijiwa; Ángel López García-Arias; Yasuyuki Okoshi; Kazushi Kawamura; Thiem Van Chu; Daichi Fujiki; Susumu Takeuchi; Masato Motomura (Trans. Mach. Learn. Res., 2025)

Annealed Mean Field Descent Is Highly Effective for Quadratic Unconstrained Binary Optimization. - Kyo Kuroki; Thiem Van Chu; Masato Motomura; Kazushi Kawamura (CoRR, 2025)

DMSA: An Efficient Architecture for Sparse-Sparse Matrix Multiplication Based on Distribute-Merge Product Dataflow. - Yuta Nagahara; Jiale Yan; Kazushi Kawamura; Daichi Fujiki; Masato Motomura; Thiem Van Chu (IEEE Trans. Very Large Scale Integr. Syst., 2025)