A modular architecture for a 6.4-Gbyte/s, 8-Mb DRAM-integrated media chip. - Takao Watanabe; Ryo Fujita; Kazumasa Yanagisawa; Hitoshi Tanaka; Kazushige Ayukawa; Mitsuru Soga; Yuji Tanaka; Yoshimitsu Sugie; Yoshinobu Nakagome (IEEE J. Solid State Circuits, 1997)

An access-sequence control scheme to enhance random-access performance of embedded DRAM's. - Kazushige Ayukawa; Takao Watanabe; Susumu Narita (IEEE J. Solid State Circuits, 1998)

A dynamic-SDRAM-mode-control scheme for low-power systems with a 32-bit RISC CPU. - Seiji Miura; Kazushige Ayukawa; Takao Watanabe (ISLPED, 2001)