A 120-mm2 64-Mb NAND flash memory achieving 180 ns/Byte effective program speed. - Jin-Ki Kim; Koji Sakui; Sung-Soo Lee; Yasuo Itoh; Suk-Chon Kwon; Kazuhisa Kanazawa; Ki-Jun Lee; Hiroshi Nakamura; Kang-Young Kim; Toshihiko Himeno; Jang-Rae Kim; Kazushige Kanda; et al. (IEEE J. Solid State Circuits, 1997)

A 130-mm/2, 256-Mbit NAND flash with shallow trench isolation technology. - Kenichi Imamiya; Yoshihisa Sugiura; Hiroshi Nakamura; Toshihiko Himeno; Ken Takeuchi; Tamio Ikehashi; Kazushige Kanda; Koji Hosono; Riichiro Shirota; Seiichi Aritome; Kazuhiro Shimizu; Kazuo Hatakeyama; et al. (IEEE J. Solid State Circuits, 1999)

A 125-mm2 1-Gb NAND flash memory with 10-MByte/s program speed. - Kenichi Imamiya; Hiroshi Nakamura; Toshihiko Himeno; Toshio Yamamura; Tamio Ikehashi; Ken Takeuchi; Kazushige Kanda; Koji Hosono; Takuya Futatsuyama; Koichi Kawai; Riichiro Shirota; Norihisa Arai; et al. (IEEE J. Solid State Circuits, 2002)

A 120mm2 16Gb 4-MLC NAND Flash Memory with 43nm CMOS Technology. - Kazushige Kanda; Masaru Koyanagi; Toshio Yamamura; Koji Hosono; Masahiro Yoshihara; Toru Miwa; Yosuke Kato; Alex Mak; Siu Lung Chan; Frank Tsai; Raul Cernea; Binh Le; et al. (ISSCC, 2008)

A 19nm 112.8mm2 64Gb multi-level flash memory with 400Mb/s/pin 1.8V Toggle Mode interface. - Noboru Shibata; Kazushige Kanda; Toshiki Hisada; Katsuaki Isobe; Manabu Sato; Yui Shimizu; Takahiro Shimizu; Takahiro Sugimoto; Tomohiro Kobayashi; Kazuko Inuzuka; Naoaki Kanagawa; Yasuyuki Kajitani; et al. (ISSCC, 2012)

An Embedded DRAM Technology for High-Performance NAND Flash Memories. - Daisaburo Takashima; Mitsuhiro Noguchi; Noboru Shibata; Kazushige Kanda; Hiroshi Sukegawa; Shuso Fujii (IEEE J. Solid State Circuits, 2012)

A 19 nm 112.8 mm2 64 Gb Multi-Level Flash Memory With 400 Mbit/sec/pin 1.8 V Toggle Mode Interface. - Kazushige Kanda; Noboru Shibata; Toshiki Hisada; Katsuaki Isobe; Manabu Sato; Yui Shimizu; Takahiro Shimizu; Takahiro Sugimoto; Tomohiro Kobayashi; Naoaki Kanagawa; Yasuyuki Kajitani; Takeshi Ogawa; et al. (IEEE J. Solid State Circuits, 2013)

A 512Gb 3b/Cell 3D flash memory on a 96-word-line-layer technology. - Hiroshi Maejima; Kazushige Kanda; Susumu Fujimura; Teruo Takagiwa; Susumu Ozawa; Jumpei Sato; Yoshihiko Shindo; Manabu Sato; Naoaki Kanagawa; Junji Musha; Satoshi Inoue; Katsuaki Sakurai; et al. (ISSCC, 2018)

A 1.33Tb 4-bit/Cell 3D-Flash Memory on a 96-Word-Line-Layer Technology. - Noboru Shibata; Kazushige Kanda; Takahiro Shimizu; Jun Nakai; Osamu Nagao; Naoki Kobayashi 004; Makoto Miakashi; Yasushi Nagadomi; Takeshi Nakano; Takahisa Kawabe; Taira Shibuya; Mario Sako; et al. (ISSCC, 2019)

A 1.33-Tb 4-Bit/Cell 3-D Flash Memory on a 96-Word-Line-Layer Technology. - Noboru Shibata; Takahisa Kawabe; Taira Shibuya; Mario Sako; Kosuke Yanagidaira; Toshifumi Hashimoto; Hiroki Date; Manabu Sato; Tomoki Nakagawa; Junji Musha; Takatoshi Minamoto; Kazushige Kanda; et al. (IEEE J. Solid State Circuits, 2020)

A 1-Tb 4b/Cell 4-Plane 162-Layer 3D Flash Memory With a 2.4-Gb/s I/O Speed Interface. - Jong Yuh; Jason Li 001; Heguang Li; Yoshihiro Oyama; Cynthia Hsu; Pradeep Anantula; Stanley Jeong; Anirudh Amarnath; Siddhesh Darne; Sneha Bhatia; Tianyu Tang; Aditya Arya; et al. (ISSCC, 2022)

A 1-Tb 4-b/cell 4-Plane 162-Layer 3-D Flash Memory With 2.4-Gb/s IO Interface. - Jonghak Yuh; Yen-Lung Jason Li; Heguang Li; Yoshihiro Oyama; Cynthia Hsu; Pradeep Anantula; Gwang Yeong Stanley Jeong; Anirudh Amarnath; Siddhesh Darne; Sneha Bhatia; Tianyu Tang; Aditya Arya; et al. (IEEE J. Solid State Circuits, 2023)