TCAD/DA for MPU and ASIC Development. - Hiroo Masuda; Katsumi Tsuneno; Hisako Sato; Kazutaka Mori (ASP-DAC, 1998)

A new optimization strategy for CMOS device process in the era of 0.2 μm and beyond for MPU's and ASIC's. - Kazutaka Mori; Ken'ichi Kikushima; Fumio Ootsuka; Shin'ichiro Mitani (CICC, 1998)

Design methodology of high performance microprocessor using ultra-low threshold voltage CMOS. - Tamotsu Miyake; Takeo Yamashita; Norikatsu Asari; Hideki Sekisaka; Tom Sakai; Kazuhiro Matsuura; Atsushi Wakahara; Hideyuki Takahashi; Tom Hiyama; Kazuhisa Miyamoto; Kazutaka Mori (CICC, 2001)

A 28 nm 50% power reduced 2T mask ROM with 0.72 ns read access time using column source bias. - Yukiko Umemoto; Koji Nii; Jiro Ishikawa; Kazuyoshi Okamoto; Kazutaka Mori; Kazumasa Yanagisawa (CICC, 2011)

28 nm 50% Power-Reducing Contacted Mask Read Only Memory Macro With 0.72-ns Read Access Time Using 2T Pair Bitcell and Dynamic Column Source Bias Control Technique. - Yukiko Umemoto; Koji Nii; Jiro Ishikawa; Makoto Yabuuchi; Kazuyoshi Okamoto; Yasumasa Tsukamoto; Shinji Tanaka; Koji Tanaka; Tetsuya Matsumura; Kazutaka Mori; Kazumasa Yanagisawa (IEEE Trans. Very Large Scale Integr. Syst., 2014)