Test Pattern Considerations for Fault Tolerant High Density DRAM. - Hiroshi Miyamoto; Koichiro Mashiko; Yoshikazu Morooka; Kazutami Arimoto; Michihiro Yamada; Takao Nakano (ITC, 1985)

A New Array Architecture for Parallel Testing in VLSI Memories. - Yoshio Matsuda; Kazutami Arimoto; Masaki Tsukude; Tsukasa Oishi; Kazuyasu Fujishima (ITC, 1989)

A built-in Hamming code ECC circuit for DRAMs. - Kiyohiro Furutani; Kazutami Arimoto; Hiroshi Miyamoto; Toshifumi Kobayashi; Kenichi Yasuda; Koichiro Mashiko (IEEE J. Solid State Circuits, 1989)

A 60-ns 3.3-V-only 16-Mbit DRAM with multipurpose register. - Kazutami Arimoto; Kazuyasu Fujishima; Yoshio Matsuda; Masaki Tsukude; Tukasa Oishi; Wataru Wakamiya; Shin'ichi Satoh 004; Michihiro Yamada; Takao Nakano (IEEE J. Solid State Circuits, 1989)

A speed-enhanced DRAM array architecture with embedded ECC. - Kazutami Arimoto; Yoshio Matsuda; Kiyohiro Furutani; Masaki Tsukude; Tsukasa Ooishi; Koichiro Mashiko; Kuzuyasu Fujishima (IEEE J. Solid State Circuits, 1990)

A circuit design of intelligent cache DRAM with automatic write-back capability. - Kazutami Arimoto; Mikio Asakura; Hideto Hidaka; Yoshio Matsuda; Kazuyasu Fujishima (IEEE J. Solid State Circuits, 1991)

A Testing Technique for ULSI Memory with On-Chip Voltage Down Converter. - Masaki Tsukude; Kazutami Arimoto; Hideto Hidaka; Yasuhiro Konishi; Masanori Hayashikoshi; Katsunori Suma; Kazuyasu Fujishima (ITC, 1992)

Cell-plate line connecting complementary bit-line (C3) architecture for battery-operated DRAMs. - Mikio Asakura; Kazutami Arimoto; Hideto Hidaka; Kazuyasu Fujishima (IEEE J. Solid State Circuits, 1992)

A dual-mode sensing scheme of capacitor-coupled EEPROM cell. - Masanori Hayashikoshi; Hideto Hidaka; Kazutami Arimoto; Kazuyasu Fujishima (IEEE J. Solid State Circuits, 1992)

A high-density dual-port memory cell operation and array architecture for ULSI DRAMs. - Hideto Hidaka; Kazutami Arimoto; Kazuyasu Fujishima (IEEE J. Solid State Circuits, 1992)

A 34-ns 16-Mb DRAM with controllable voltage down-converter. - Hideto Hidaka; Kazutami Arimoto; Kazutoshi Hirayama; Masanori Hayashikoshi; Mikio Asakura; Masaki Tsukude; Tsukasa Oishi; Shinji Kawai; Katsuhiro Suma; Yasuhiro Konishi; Koji Tanaka; Wataru Wakamiya; et al. (IEEE J. Solid State Circuits, 1992)

Highly Reliable Testing of ULSI Memories with On-Chip Voltage-Down Converters. - Masaki Tsukude; Kazutami Arimoto; Hideto Hidaka; Yasuhiro Konishi; Masanori Hayashikoshi; Katsuhiro Suma; Kazuyasu Fujishima (IEEE Des. Test Comput., 1993)

A well-synchronized sensing/equalizing method for sub-1.0-V operating advanced DRAMs. - Tsukasa Ooishi; Mikio Asakura; Shigeki Tomishima; Hideto Hidaka; Kazutami Arimoto; Kazuyasu Fujishima (IEEE J. Solid State Circuits, 1994)

Low voltage circuit design techniques for battery-operated and/or giga-scale DRAMs. - Tadato Yamagata; Shigeki Tomishima; Masaki Tsukude; Takahiro Tsuruda; Yasushi Hashizume; Kazutami Arimoto (IEEE J. Solid State Circuits, 1995)

SOI-DRAM circuit technologies for low power high speed multigiga scale memories. - Shigehiro Kuge; Fukashi Morishita; Takahiro Tsuruda; Shigeki Tomishima; Masaki Tsukude; Tadato Yamagata; Kazutami Arimoto (IEEE J. Solid State Circuits, 1996)

A 1.6-GB/s data-rate 1-Gb synchronous DRAM with hierarchical square-shaped memory block and distributed bank architecture. - Narumi Sakashita; Yasuhiko Nitta; Ken'ichi Shimomura; Fumihiro Okuda; Hiroki Shimano; Satoshi Yamakawa; Masaki Tsukude; Kazutami Arimoto; Shinji Baba; Shinji Komori; Kazuo Kyuma; Akihiko Yasuoka; et al. (IEEE J. Solid State Circuits, 1996)

A 1-V 46-ns 16-Mb SOI-DRAM with body control technique. - Ken'ichi Shimomura; Hiroki Shimano; Narumi Sakashita; Fumihiro Okuda; Toshiyuki Oashi; Yasuo Yamaguchi; Takahisa Eimori; Masahide Inuishi; Kazutami Arimoto; Shigeto Maegawa; Yasuo Inoue; Shinji Komori; et al. (IEEE J. Solid State Circuits, 1997)

A 1.2- to 3.3-V wide voltage-range/low-power DRAM with a charge-transfer presensing scheme. - Masaki Tsukude; Shigehiro Kuge; Takeshi Fujino; Kazutami Arimoto (IEEE J. Solid State Circuits, 1997)

High-speed/high-bandwidth design methodologies for on-chip DRAM core multimedia system LSI's. - Takahiro Tsuruda; Mako Kobayashi; Masaki Tsukude; Tadato Yamagata; Kazutami Arimoto; Michihiro Yamada (IEEE J. Solid State Circuits, 1997)

400-MHz random column operating SDRAM techniques with self-skew compensation. - Takeshi Hamamoto; Masaki Tsukude; Kazutami Arimoto; Yasuhiro Konishi; Takayuki Miyamoto; Hideyuki Ozaki; Michihiro Yamada (IEEE J. Solid State Circuits, 1998)

A 5.3-GB/s embedded SDRAM core with slight-boost scheme. - Akira Yamazaki; Tadato Yamagata; Makoto Hatakenaka; Atsushi Miyanishi; Isao Hayashi; Shigeki Tomishima; Atsuo Mangyo; Yoshio Yukinari; Takashi Tatsumi; Masashi Matsumura; Kazutami Arimoto; Michihiro Yamada (IEEE J. Solid State Circuits, 1999)

High-performance embedded SOI DRAM architecture for the low-power supply. - Tadaaki Yamauchi; Fukashi Morishita; Shigenobu Maeda; Kazutami Arimoto; Kazuyasu Fujishima; Hideyuki Ozaki; Tsutomu Yoshihara (IEEE J. Solid State Circuits, 2000)

Test cost reduction by at-speed BISR for embedded DRAMs. - Yoshihiro Nagura; Michael Mullins; Anthony Sauvageau; Yoshinoro Fujiwara; Katsuya Furue; Ryuji Ohmura; Tatsunori Komoike; Takenori Okitaka; Tetsushi Tanizaki; Katsumi Dosaka; Kazutami Arimoto; Yukiyoshi Koda; et al. (ITC, 2001)

Design methodology of embedded DRAM with virtual-socket architecture. - Tadaaki Yamauchi; Mitsuya Kinoshita; Teruhiko Amano; Katsumi Dosaka; Kazutami Arimoto; Hideyuki Ozaki; Michihiro Yamada; Tsutomu Yoshihara (IEEE J. Solid State Circuits, 2001)

A Low Power Embedded DRAM Macro for Battery-Operated LSIs. - Takeshi Fujino; Akira Yamazaki; Yasuhiko Taito; Mitsuya Kinoshita; Fukashi Morishita; Teruhiko Amano; Masaru Haraguchi; Makoto Hatakenaka; Atsushi Amo; Atsushi Hachisuka; Kazutami Arimoto; Hideyuki Ozaki (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003)

An embedded DRAM with a 143-MHz SRAM interface using a sense-synchronized read/write. - Yasuhiko Taito; Tetsushi Tanizaki; Mitsuya Kinoshita; Futoshi Igaue; Takeshi Fujino; Kazutami Arimoto (IEEE J. Solid State Circuits, 2003)

A capacitorless twin-transistor random access memory (TTRAM) on SOI. - Fukashi Morishita; Hideyuki Noda; Takayuki Gyohten; Mako Okamoto; Takashi Ipposhi; Shigeto Maegawa; Katsumi Dosaka; Kazutami Arimoto (CICC, 2005)

A soft-error-immune maintenance-free TCAM architecture with associated embedded DRAM. - Hideyuki Noda; Katsumi Dosaka; Fukashi Morishita; Kazutami Arimoto (CICC, 2005)

CAM-based VLSI architecture for Huffman coding with real-time optimization of the code word table [image coding example]. - Takeshi Kumaki; Yasuto Kuroda; Tetsushi Koide; Hans Jürgen Mattausch; Hideyuki Noda; Katsumi Dosaka; Kazutami Arimoto; Kazunori Saito (ISCAS (5), 2005)

A CAM-Based Signature-Matching Co-processor with Application-Driven Power-Reduction Features. - Kazunari Inoue; Hideyuki Noda; Kazutami Arimoto; Hans Jürgen Mattausch; Tetsushi Koide (IEICE Trans. Electron., 2005)

Embedded Low-Power Dynamic TCAM Architecture with Transparently Scheduled Refresh. - Hideyuki Noda; Kazunari Inoue; Hans Jürgen Mattausch; Tetsushi Koide; Katsumi Dosaka; Kazutami Arimoto; Kazuyasu Fujishima; Kenji Anami; Tsutomu Yoshihara (IEICE Trans. Electron., 2005)

A Study of Sense-Voltage Margins in Low-Voltage-Operating Embedded DRAM Macros. - Akira Yamazaki; Fukashi Morishita; Naoya Watanabe; Teruhiko Amano; Masaru Haraguchi; Hideyuki Noda; Atsushi Hachisuka; Katsumi Dosaka; Kazutami Arimoto; Setsuo Wake; Hideyuki Ozaki; Tsutomu Yoshihara (IEICE Trans. Electron., 2005)

A 322 MHz random-cycle embedded DRAM with high-accuracy sensing and tuning. - Masahisa Iida; Naoki Kuroda; Hidefumi Otsuka; Masanobu Hirose; Yuji Yamasaki; Kiyoto Ohta; Kazuhiko Shimakawa; Takashi Nakabayashi; Hiroyuki Yamauchi; Tomohiko Sano; Takayuki Gyohten; Masanao Maruta; et al. (IEEE J. Solid State Circuits, 2005)

A 312-MHz 16-Mb random-cycle embedded DRAM macro with a power-down data retention mode for mobile applications. - Fukashi Morishita; Isamu Hayashi; Hideto Matsuoka; Kazuhiro Takahashi; Kuniyasu Shigeta; Takayuki Gyohten; Mitsutaka Niiro; Hideyuki Noda; Mako Okamoto; Atsushi Hachisuka; Atsushi Amo; Hiroki Shinkawata; et al. (IEEE J. Solid State Circuits, 2005)

A cost-efficient high-performance dynamic TCAM with pipelined hierarchical searching and shift redundancy architecture. - Hideyuki Noda; Kazunari Inoue; Masayuki Kuroiwa; Futoshi Igaue; Kouji Yamamoto 002; Hans Jürgen Mattausch; Tetsushi Koide; Atsushi Amo; Atsushi Hachisuka; Shinya Soeda; Isamu Hayashi; Fukashi Morishita; et al. (IEEE J. Solid State Circuits, 2005)

A Scalable ET2RAM (SETRAM) with Verify Control for SoC Platform Memory IP on SOI. - Kazutami Arimoto; Fukashi Morishita; Isamu Hayashi; Tetsushi Tanizaki; Takashi Ipposhi; Katsumi Dosaka (CICC, 2006)

A 40GOPS 250mW massively parallel processor based on matrix architecture. - Masami Nakajima; Hideyuki Noda; Katsumi Dosaka; Kiyoshi Nakata; Motoki Higashida; Osamu Yamamoto; Katsuya Mizumoto; Hiroyuki Kondo; Yukihiko Shimazu; Kazutami Arimoto; Kazunori Saitoh; Toru Shimizu (ISSCC, 2006)

An On-Chip Supply-Voltage Control System Considering PVT Variations for Worst-Caseless Lower Voltage SoC Design. - Takayuki Gyohten; Fukashi Morishita; Isamu Hayashi; Mako Okamoto; Hideyuki Noda; Katsumi Dosaka; Kazutami Arimoto; Yasutaka Horiba (IEICE Trans. Electron., 2006)

A Reliability-Enhanced TCAM Architecture with Associated Embedded DRAM and ECC. - Hideyuki Noda; Katsumi Dosaka; Hans Jürgen Mattausch; Tetsushi Koide; Fukashi Morishita; Kazutami Arimoto (IEICE Trans. Electron., 2006)

Efficient Vertical/Horizontal-Space 1D-DCT Processing Based on Massive-Parallel Matrix-Processing Engine. - Takeshi Kumaki; Tetsushi Koide; Hans Jürgen Mattausch; Yasuto Kuroda; Hideyuki Noda; Katsumi Dosaka; Kazutami Arimoto; Kazunori Saito (ISCAS, 2007)

Design of a Processing Element Based on Quaternary Differential Logic for a Multi-Core SIMD Processor. - Hirokatsu Shirahama; Akira Mochizuki; Takahiro Hanyu; Masami Nakajima; Kazutami Arimoto (ISMVL, 2007)

A Continuous-Adaptive DDR2 Interface with Flexible Round-Trip-Time and Full Self Loop-Backed AC Test. - Masaru Haraguchi; Tokuya Osawa; Akira Yamazaki; Chikayoshi Morishima; Toshinori Morihara; Yoshikazu Morooka; Yoshihiro Okuno; Kazutami Arimoto (ISSCC, 2007)

Continuous Design Efforts for Ubiquitous Network Era under the Physical Limitation of Advanced CMOS. - Kazutami Arimoto; Toshihiro Hattori; Hidehiro Takata; Atsushi Hasegawa; Toru Shimizu (IEICE Trans. Electron., 2007)

Acceleration of DCT Processing with Massive-Parallel Memory-Embedded SIMD Matrix Processor. - Takeshi Kumaki; Masakatsu Ishizaki; Tetsushi Koide; Hans Jürgen Mattausch; Yasuto Kuroda; Hideyuki Noda; Katsumi Dosaka; Kazutami Arimoto; Kazunori Saito (IEICE Trans. Inf. Syst., 2007)

Real-Time Huffman Encoder with Pipelined CAM-Based Data Path and Code-Word-Table Optimizer. - Takeshi Kumaki; Yasuto Kuroda; Masakatsu Ishizaki; Tetsushi Koide; Hans Jürgen Mattausch; Hideyuki Noda; Katsumi Dosaka; Kazutami Arimoto; Kazunori Saito (IEICE Trans. Inf. Syst., 2007)

A Capacitorless Twin-Transistor Random Access Memory (TTRAM) on SOI. - Fukashi Morishita; Hideyuki Noda; Isamu Hayashi; Takayuki Gyohten; Mako Okamoto; Takashi Ipposhi; Shigeto Maegawa; Katsumi Dosaka; Kazutami Arimoto (IEICE Trans. Electron., 2007)

A Voltage Scalable Advanced DFM RAM with Accelerated Screening for Low Power SoC Platform. - Hiroki Shimano; Fukashi Morishita; Katsumi Dosaka; Kazutami Arimoto (IEICE Trans. Electron., 2007)

A High-Density Scalable Twin Transistor RAM (TTRAM) With Verify Control for SOI Platform Memory IPs. - Kazutami Arimoto; Fukashi Morishita; Isamu Hayashi; Katsumi Dosaka; Hiroki Shimano; Takashi Ipposhi (IEEE J. Solid State Circuits, 2007)

A Configurable Enhanced TTRAM Macro for System-Level Power Management Unified Memory. - Fukashi Morishita; Isamu Hayashi; Takayuki Gyohten; Hideyuki Noda; Takashi Ipposhi; Hiroki Shimano; Katsumi Dosaka; Kazutami Arimoto (IEEE J. Solid State Circuits, 2007)

The Design and Implementation of the Massively Parallel Processor Based on the Matrix Architecture. - Hideyuki Noda; Masami Nakajima; Katsumi Dosaka; Kiyoshi Nakata; Motoki Higashida; Osamu Yamamoto; Katsuya Mizumoto; Tetsushi Tanizaki; Takayuki Gyohten; Yoshihiro Okuno; Hiroyuki Kondo; Yukihiko Shimazu; et al. (IEEE J. Solid State Circuits, 2007)

The Circuits and Robust Design Methodology of the Massively Parallel Processor Based on the Matrix Architecture. - Hideyuki Noda; Tetsushi Tanizaki; Takayuki Gyohten; Katsumi Dosaka; Masami Nakajima; Katsuya Mizumoto; Kanako Yoshida; Takenobu Iwao; Tetsu Nishijima; Yoshihiro Okuno; Kazutami Arimoto (IEEE J. Solid State Circuits, 2007)

Heterogeneous multicore SoC for secure multimedia applications. - Hiroyuki Kondo; Masami Nakajima; Sugako Otani; Osamu Yamamoto; Norio Masui; Naoto Okumura; Mamoru Sakugawa; Masaya Kitao; Koichi Ishimi; Masayuki Sato; Fumitaka Fukuzawa; Kazuhiro Inaoka; et al. (CICC, 2008)

Integration Architecture of Content Addressable Memory and Massive-Parallel Memory-Embedded SIMD Matrix for Versatile Multimedia Processor. - Takeshi Kumaki; Masakatsu Ishizaki; Tetsushi Koide; Hans Jürgen Mattausch; Yasuto Kuroda; Takayuki Gyohten; Hideyuki Noda; Katsumi Dosaka; Kazutami Arimoto; Kazunori Saito (IEICE Trans. Electron., 2008)

Design and Implementation of a Configurable Heterogeneous Multicore SoC With Nine CPUs and Two Matrix Processors. - Hiroyuki Kondo; Masami Nakajima; Norio Masui; Sugako Otani; Naoto Okumura; Yukari Takata; Takashi Nasu; Hirokazu Takata; Takashi Higuchi; Mamoru Sakugawa; Hayato Fujiwara; Kazuya Ishida; et al. (IEEE J. Solid State Circuits, 2008)

A Continuous-Adaptive DDRx Interface with Flexible Round-Trip-Time and Full Self Loop-Backed AC Test. - Masaru Haraguchi; Tokuya Osawa; Akira Yamazaki; Chikayoshi Morishima; Toshinori Morihara; Yoshikazu Morooka; Yoshihiro Okuno; Kazutami Arimoto (IEICE Trans. Electron., 2009)

On-Chip Memory Power-Cut Scheme Suitable for Low Power SoC Platform. - Hiroki Shimano; Fukashi Morishita; Katsumi Dosaka; Kazutami Arimoto (IEICE Trans. Electron., 2009)

Heterogeneous Multicore SoC With SiP for Secure Multimedia Applications. - Hiroyuki Kondo; Sugako Otani; Masami Nakajima; Osamu Yamamoto; Norio Masui; Naoto Okumura; Mamoru Sakugawa; Masaya Kitao; Koichi Ishimi; Masayuki Sato; Fumitaka Fukuzawa; Satoshi Imasu; et al. (IEEE J. Solid State Circuits, 2009)

PEARL: Power-Aware, Dependable, and High-Performance Communication Link Using PCI Express. - Toshihiro Hanawa; Taisuke Boku; Shin'ichi Miura; Mitsuhisa Sato; Kazutami Arimoto (GreenCom/CPSCom, 2010)

A scalable massively parallel processor for real-time image processing. - Takashi Kurafuji; Masaru Haraguchi; Masami Nakajima; Takayuki Gyohten; Tetsu Nishijima; Hiroyuki Yamasaki; Yuta Imai; Masakatsu Ishizaki; Takeshi Kumaki; Yoshihiro Okuno; Tetsushi Koide; Hans Jürgen Mattausch; et al. (ISSCC, 2010)

Fusion of MEMS and circuits. - Satoshi Shigematsu; Kazutami Arimoto; Christoph Hagleitner (ISSCC, 2010)

Dependable SRAM with enhanced read-/write-margins by fine-grained assist bias control for low-voltage operation. - Koji Nii; Makoto Yabuuchi; Hidehiro Fujiwara; Hirofumi Nakano; Kazuya Ishihara; Hiroyuki Kawai; Kazutami Arimoto (SoCC, 2010)

An 80 Gbps dependable multicore communication SoC with PCI express I/F and intelligent interrupt controller. - Sugako Otani; Hiroyuki Kondo; Itaru Nonomura; Atsuyuki Ikeya; Minoru Uemura; Katsushi Asahina; Kazutami Arimoto; Shin'ichi Miura; Toshihiro Hanawa; Taisuke Boku; Mitsuhisa Sato (COOL Chips, 2011)

Implementation and evaluation of FAST corner detection on the massively parallel embedded processor MX-G. - Yushi Moko; Yoshihiro Watanabe; Takashi Komuro; Masatoshi Ishikawa; Masami Nakajima; Kazutami Arimoto (CVPR Workshops, 2011)

PEARL and PEACH: A Novel PCI Express Direct Link and Its Implementation. - Toshihiro Hanawa; Taisuke Boku; Shin'ichi Miura; Mitsuhisa Sato; Kazutami Arimoto (IPDPS Workshops, 2011)

An 80Gb/s dependable communication SoC with PCI express I/F and 8 CPUs. - Sugako Otani; Hiroyuki Kondo; Itaru Nonomura; Atsuyuki Ikeya; Minoru Uemura; Yasushi Hayakawa; Takeshi Oshita; Satoshi Kaneko; Katsushi Asahina; Kazutami Arimoto; Shin'ichi Miura; Toshihiro Hanawa; et al. (ISSCC, 2011)

Low Power Platform for Embedded Processor LSIs. - Toru Shimizu; Kazutami Arimoto; Osamu Nishii; Sugako Otani; Hiroyuki Kondo (IEICE Trans. Electron., 2011)

A Scalable Massively Parallel Processor for Real-Time Image Processing. - Takashi Kurafuji; Masaru Haraguchi; Masami Nakajima; Tetsu Nishijima; Tetsushi Tanizaki; Hiroyuki Yamasaki; Takeaki Sugimura; Yuta Imai; Masakatsu Ishizaki; Takeshi Kumaki; Kan Murata; Kanako Yoshida; et al. (IEEE J. Solid State Circuits, 2011)

What's next in robots? ∼Sensing, processing, networking toward human brain and body. - Kazutami Arimoto; Sam Kavusi; Kenneth Salisbury (ISSCC, 2012)

Consistency Verification of UML Diagrams Based on Process Bisimulation. - Tomoyuki Yokogawa; Sousuke Amasaki; Keisuke Okazaki; Yoichiro Sato; Kazutami Arimoto; Hisashi Miyazaki (PRDC, 2013)

Low-Power On-Chip Charge-Recycling DC-DC Conversion Circuit and System. - Kazuhiro Ueda; Fukashi Morishita; Shunsuke Okura; Leona Okamura; Tsutomu Yoshihara; Kazutami Arimoto (IEEE J. Solid State Circuits, 2013)

The LSI implementation of a memory based field programmable device for MCU peripherals. - Tetsuya Matsumura; Naoya Okada; Yoshifumi Kawamura; Koji Nii; Kazutami Arimoto; Hiroshi Makino; Yoshio Matsuda (DDECS, 2014)

F5: Low-power radios for sensor networks. - Woogeun Rhee; Gangadhar Burra; Kazutami Arimoto; Pieter Harpe; Brian Otis; David Ruffieux (ISSCC, 2014)

Bounded model checking of Time Petri Nets using SAT solver. - Tomoyuki Yokogawa; Masafumi Kondo; Hisashi Miyazaki; Sousuke Amasaki; Yoichiro Sato; Kazutami Arimoto (IEICE Electron. Express, 2015)

A Serial Booth Multiplier Using Ring Oscillator. - Daichi Okamoto; Masafumi Kondo; Tomoyuki Yokogawa; Yoshihiro Sejima; Kazutami Arimoto; Yoichiro Sato (CANDAR, 2016)

3D2 processing architecture - High reliability and low power computing for novel nano tactile sensor array. - Kiyotaka Komoku; Kazutami Arimoto; Tomoyuki Yokogawa; Hitoshi Yamauchi; Yoichiro Sato; Hidekuni Takao (ISOCC, 2016)

A Field Programmable Sequencer and Memory with Middle Grained Programmability Optimized for MCU Peripherals. - Yoshifumi Kawamura; Naoya Okada; Yoshio Matsuda; Tetsuya Matsumura; Hiroshi Makino; Kazutami Arimoto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016)

A smart low power R-R-I heartbeat monitor system with contactless UWB sensor. - Kazutami Arimoto; Daichi Yamashita; Nao Igawa; Tomoyuki Yokogawa; Yoichiro Sato; Isao Kayano; Akio Shiratori (ISOCC, 2017)

Tool Support for Consistency Verification of UML Diagrams. - Salilthip Phuklang; Tomoyuki Yokogawa; Pattara Leelaprute; Kazutami Arimoto (PROFES, 2017)

Interpolation Based Unbounded Model Checking for Time Petri Nets. - Nao Igawa; Tomoyuki Yokogawa; Sousuke Amasaki; Kiyotaka Komoku; Yoichiro Sato; Kazutami Arimoto (GCCE, 2018)

Radio link design for ITS integrated network using drone. - Satoshi Fujii; Issei Nakaema; Kei Miyagi; Shouichiro Tanifuji; Noriaki Yoshikawa; Kensaku Kinoshita; Kazutami Arimoto (APWCS, 2019)

A Compact Low Power AI Module Mounted on Drone for Plant Monitor System. - Tomoki Kobayashi; Tomoyuki Yokogawa; Nao Igawa; Yoichiro Sato; Satoshi Fujii; Kazutami Arimoto (IIAI-AAI, 2019)

Consistency Verification of UML Sequence Diagrams Modeling Wireless Sensor Networks. - Akira Matsumoto; Tomoyuki Yokogawa; Sousuke Amasaki; Hirohisa Aman; Kazutami Arimoto (IIAI-AAI, 2019)

A Node-Style Visual Programming Environment for the nuXmv Model Checker. - Hayato Naito; Tomoyuki Yokogawa; Nao Igawa; Sousuke Amasaki; Hirohisa Aman; Kazutami Arimoto (GCCE, 2020)

Model Checking of Visual Scripts Created by UE4 Blueprints. - Nao Igawa; Tomoyuki Yokogawa; Mami Takahashi; Kazutami Arimoto (IIAI-AAI, 2020)

A Edge Master Computing for Pineapple Monitoring System with Drone and Data-management. - Tomoki Kobayashi; Tomoyuki Yokogawa; Nao Igawa; Yoichiro Sato; Kimihoro Sugino; Hiroshi Miyata; Satoshi Fujii; Kazutami Arimoto (IIAI-AAI, 2020)

Symbolic Representation of Time Petri Nets for Efficient Bounded Model Checking. - Nao Igawa; Tomoyuki Yokogawa; Sousuke Amasaki; Masafumi Kondo; Yoichiro Sato; Kazutami Arimoto (IEICE Trans. Inf. Syst., 2020)

New Value Creation by Nano-Tactile Sensor Chip Exceeding our Fingertip Discrimination Ability. - Hidekuni Takao; Kazuki Watatani; Kazutami Arimoto (HCS, 2021)

Localized Data Transfer System by Vehicles and Cellular Base Station in Local Area. - Hiroshi Miyata; Kazutami Arimoto (ICC Workshops, 2021)

A Visual Modeling Environment for the nuXmv Model Checker Intended for Novice Users. - Kazuma Toyota; Tomoyuki Yokogawa; Sousuke Amasaki; Hirohisa Aman; Kazutami Arimoto (IIAI-AAI, 2022)

Verifying Game Logic in Unreal Engine 5 Blueprint Visual Scripting System Using Model Checking. - Kazuki Wayama; Tomoyuki Yokogawa; Sousuke Amasaki; Hirohisa Aman; Kazutami Arimoto (ASE, 2022)

28-m W Fully Embedded AI Techniques with On-site Learning for Low-Power Handy Tactile Sensing System. - Yuji Yano; Hisashi Iwamoto; Takuma Yoshimura; Yoshihiro Nishida; Tatsuya Mori; Kiyotaka Komoku; Hidekuni Takao; Kazutami Arimoto (VLSI-DAT, 2022)

Applying Symbolic Model Checking to Node-graph Style Game Scripts with Time Constraints. - Ryugo Tanaka; Tomoyuki Yokogawa; Sousuke Amasaki; Hirohisa Aman; Kazutami Arimoto (GCCE, 2023)

Enhancing the Generalization Performance of Drowsiness Estimation AI in Drivers Using Time-Series Data from FAUs with Limited Datasets. - Tomoya Kubo; Tomoyuki Yokogawa; Kazutami Arimoto; Masaki Hokari; Isao Kayano (IIAI-AAI-Winter, 2023)

Distributed Hierarchical AI Architecture for Meta-Described Local Dynamic Maps in Autonomous Driving. - Hiroshi Miyata; Kazutami Arimoto; Masatoshi Saitoh; Atsushi Hayami; Hisayoshi Mizuno; Yukihiko Shimazu; Tomoyuki Yokogawa (IIAI-AAI, 2024)