Unequal Error Protection Codes with Two-Level Burst and Bit Error Correcting Capabilities. - Kazuteru Namba; Eiji Fujiwara (DFT, 2001)

A class of systematic m-ary single-symbol error correcting codes. - Kazuteru Namba; Eiji Fujiwara (Syst. Comput. Jpn., 2001)

Two-Level Unequal Error Protection Codes with Burst and Bit Error Correcting Capabilities. - Kazuteru Namba; Eiji Fujiwara (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002)

Design of Defect Tolerant Wallace Multiplier. - Kazuteru Namba; Hideo Ito (PRDC, 2005)

Deterministic Delay Fault BIST Using Adjacency Test Pattern Generation. - Kazuteru Namba; Hideo Ito (IEICE Trans. Inf. Syst., 2005)

Scan Design for Two-Pattern Test without Extra Latches. - Kazuteru Namba; Hideo Ito (IEICE Trans. Inf. Syst., 2005)

Interleaving of Delay Fault Tes Data for Efficient Test Compression with Statistical Coding. - Kazuteru Namba; Hideo Ito (ATS, 2006)

Soft Error Masking Circuit and Latch Using Schmitt Trigger Circuit. - Yoichi Sasaki 001; Kazuteru Namba; Hideo Ito (DFT, 2006)

Proposal of Testable Multi-Context FPGA Architecture. - Kazuteru Namba; Hideo Ito (IEICE Trans. Inf. Syst., 2006)

Redundant Design for Wallace Multiplier. - Kazuteru Namba; Hideo Ito (IEICE Trans. Inf. Syst., 2006)

Soft Error Hardened Latch Scheme for Enhanced Scan Based Delay Fault Testing. - Takashi Ikeda; Kazuteru Namba; Hideo Ito (DFT, 2007)

Nonbinary single-symbol error correcting, adjacent two-symbol transposition error correcting codes over integer rings. - Kazuteru Namba; Eiji Fujiwara (Syst. Comput. Jpn., 2007)

Delay Fault Testability on Two-Rail Logic Circuits. - Kazuteru Namba; Hideo Ito (DFT, 2008)

Soft Error Hardened FF Capable of Detecting Wide Error Pulse. - Shuangyu Ruan; Kazuteru Namba; Hideo Ito (DFT, 2008)

Path Delay Fault Test Set for Two-Rail Logic Circuits. - Kazuteru Namba; Hideo Ito (PRDC, 2008)

Circuit and Latch Capable of Masking Soft Errors with Schmitt Trigger. - Yoichi Sasaki 001; Kazuteru Namba; Hideo Ito (J. Electron. Test., 2008)

Two-Stage Stuck-at Fault Test Data Compression Using Scan Flip-Flops with Delay Fault Testability. - Kentaroh Katoh; Kazuteru Namba; Hideo Ito (IPSJ Trans. Syst. LSI Des. Methodol., 2008)

A Delay Measurement Technique Using Signature Registers. - Kentaroh Katoh; Toru Tanabe; Haque Md Zahidul; Kazuteru Namba; Hideo Ito (Asian Test Symposium, 2009)

Testing of Switch Blocks in Three-Dimensional FPGA. - Takumi Hoshi; Kazuteru Namba; Hideo Ito (DFT, 2009)

Dependability Evaluation for Internet-Based Remote Systems. - Masato Kitakami; Akihiro Katada; Kazuteru Namba; Hideo Ito (PRDC, 2009)

Test Compression for IP Core Testing with Reconfigurable Network and Fixing-Flipping Coding. - Kazuteru Namba; Yoshikazu Matsui; Hideo Ito (J. Electron. Test., 2009)

Design for Delay Fault Testability of 2-Rail Logic Circuits. - Kentaroh Katoh; Kazuteru Namba; Hideo Ito (IEICE Trans. Inf. Syst., 2009)

Design for Delay Fault Testability of Dual Circuits Using Master and Slave Scan Paths. - Kentaroh Katoh; Kazuteru Namba; Hideo Ito (IEICE Trans. Inf. Syst., 2009)

Test Compression for Robust Testable Path Delay Fault Testing Using Interleaving and Statistical Coding. - Kazuteru Namba; Hideo Ito (IEICE Trans. Inf. Syst., 2009)

Analysis of Path Delay Fault Testability for Two-Rail Logic Circuits. - Kazuteru Namba; Hideo Ito (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

Construction of Soft-Error-Tolerant FF with Wide Error Pulse Detecting Capability. - Shuangyu Ruan; Kazuteru Namba; Hideo Ito (IEICE Trans. Inf. Syst., 2009)

A Low Area On-chip Delay Measurement System Using Embedded Delay Measurement Circuit. - Kentaroh Katoh; Kazuteru Namba; Hideo Ito (Asian Test Symposium, 2010)

Soft Error Tolerant BILBO FF. - Kazuteru Namba; Hideo Ito (DFT, 2010)

Single Event Induced Double Node Upset Tolerant Latch. - Kazuteru Namba; Masatoshi Sakata; Hideo Ito (DFT, 2010)

Quantitative Evaluation of Integrity for Remote System Using the Internet. - Masato Kitakami; Hiroshi Konno; Kazuteru Namba; Hideo Ito (PRDC, 2010)

Chiba Scan Delay Fault Testing with Short Test Application Time. - Kazuteru Namba; Hideo Ito (J. Electron. Test., 2010)

Single-Event-Upset Tolerant RS Flip-Flop with Small Area. - Kazuteru Namba; Kengo Nakashima; Hideo Ito (IEICE Trans. Inf. Syst., 2010)

Construction of SEU Tolerant Flip-Flops Allowing Enhanced Scan Delay Fault Testing. - Kazuteru Namba; Takashi Ikeda; Hideo Ito (IEEE Trans. Very Large Scale Integr. Syst., 2010)

Construction of BILBO FF with Soft-Error-Tolerant Capability. - Kazuteru Namba; Hideo Ito (IEICE Trans. Inf. Syst., 2011)

Scan FF Reordering for Test Volume Reduction in Chiba-scan Architecture. - Kiyonori Matsumoto; Kazuteru Namba; Hideo Ito (IPSJ Trans. Syst. LSI Des. Methodol., 2011)

Test Sets for Robust Path Delay Fault Testing on Two-Rail Logic Circuits. - Kazuteru Namba; Hideo Ito (IEEE Trans. Computers, 2011)

NoC Dynamically Reconfigurable as TAM. - Takieddine Sbiai; Kazuteru Namba (Asian Test Symposium, 2012)

Dual-edge-triggered FF with timing error detection capability. - Kazuteru Namba; Takashi Katagiri; Hideo Ito (DFT, 2012)

Improving small-delay fault coverage for on-chip delay measurement. - Wenpo Zhang; Kazuteru Namba; Hideo Ito (DFT, 2012)

An On-Chip Delay Measurement Technique Using Signature Registers for Small-Delay Defect Detection. - Kentaroh Katoh; Kazuteru Namba; Hideo Ito (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Testing of switch blocks in TSV-reduced Three-Dimensional FPGA. - Kouta Maebashi; Kazuteru Namba; Masato Kitakami (DFTS, 2013)

A novel scheme for concurrent error detection of OLS parallel decoders. - Kazuteru Namba; Fabrizio Lombardi (DFTS, 2013)

Extending Non-Volatile Operation to DRAM Cells. - Wei Wei 034; Kazuteru Namba; Fabrizio Lombardi (IEEE Access, 2013)

Timing-Error-Detecting Dual-Edge-Triggered Flip-Flop. - Kazuteru Namba; Takashi Katagiri; Hideo Ito (J. Electron. Test., 2013)

Design for Delay Measurement Aimed at Detecting Small Delay Defects on Global Routing Resources in FPGA. - Kazuteru Namba; Nobuhide Takashina; Hideo Ito (IEICE Trans. Inf. Syst., 2013)

Improving Test Coverage by Measuring Path Delay Time Including Transmission Time of FF. - Wenpo Zhang; Kazuteru Namba; Hideo Ito (IEICE Trans. Inf. Syst., 2013)

Designs and analysis of non-volatile memory cells for single event upset (SEU) tolerance. - Wei Wei 034; Fabrizio Lombardi; Kazuteru Namba (DFT, 2014)

New 4T-based DRAM cell designs. - Wei Wei 034; Kazuteru Namba; Fabrizio Lombardi (ACM Great Lakes Symposium on VLSI, 2014)

Scan Shift Time Reduction Using Test Compaction for On-Chip Delay Measurement. - Wenpo Zhang; Kazuteru Namba; Hideo Ito (IEICE Trans. Inf. Syst., 2014)

Improving Small-Delay Fault Coverage of On-Chip Delay Measurement by Segmented Scan and Test Point Insertion. - Wenpo Zhang; Kazuteru Namba; Hideo Ito (IEICE Trans. Inf. Syst., 2014)

Novel Designs of Embedded Hybrid Cells for High Performance Memory Circuits. - Fabrizio Lombardi; Wei Wei 034; Kazuteru Namba (ACM Great Lakes Symposium on VLSI, 2015)

A low area calibration technique of TDC using variable clock generator for accurate on-line delay measurement. - Kentaroh Katoh; Kazuteru Namba (ISQED, 2015)

Non-Binary Orthogonal Latin Square Codes for a Multilevel Phase Charge Memory (PCM). - Kazuteru Namba; Fabrizio Lombardi (IEEE Trans. Computers, 2015)

Parallel Decodable Two-Level Unequal Burst Error Correcting Codes. - Kazuteru Namba; Fabrizio Lombardi (IEEE Trans. Computers, 2015)

Construction of a soft error (SEU) hardened Latch with high critical charge. - Hiroki Ueno; Kazuteru Namba (DFT, 2016)

Design and Comparative Evaluation of a Hybrid Cache Memory at Architectural Level. - Wei Wei 034; Kazuteru Namba; Fabrizio Lombardi (ACM Great Lakes Symposium on VLSI, 2016)

A Calibration Technique for DVMC with Delay Time Controllable Inverter. - Ri Cui; Kazuteru Namba (IPSJ Trans. Syst. LSI Des. Methodol., 2016)

Single Multiscale-Symbol Error Correction Codes for Multiscale Storage Systems. - Kazuteru Namba; Fabrizio Lombardi (IEEE Trans. Computers, 2016)

Parallel Decodable Multi-Level Unequal Burst Error Correcting Codes for Memories of Approximate Systems. - Kazuteru Namba; Fabrizio Lombardi (IEEE Trans. Computers, 2016)

A Novel Scheme for Tolerating Single Event/Multiple Bit Upsets (SEU/MBU) in Non-Volatile Memories. - Wei Wei 034; Kazuteru Namba; Yong-Bin Kim; Fabrizio Lombardi (IEEE Trans. Computers, 2016)

A Coding Scheme for Write Time Improvement of Phase Change Memory (PCM) Systems. - Kazuteru Namba; Fabrizio Lombardi (IEEE Trans. Multi Scale Comput. Syst., 2016)

L band circularly polarized SAR onboard microsatellite. - Josaphat Tetuko Sri Sumantyo; Nobuyoshi Imura; Shunsuke Onishi; Tetsuo Yasaka; Robertus Heru Triharjanto; Koichi Ito 003; Steven Gao; Kazuteru Namba; Katsumi Hattori; Fumio Yamazaki; Chiharu Hongo; Akira Kato; et al. (IGARSS, 2017)

Construction of Latch Design with Complete Double Node Upset Tolerant Capability Using C-Element. - Yuta Yamamoto; Kazuteru Namba (DFT, 2018)

A Single and Adjacent Error Correction Code for Fast Decoding of Critical Bits. - Kazuteru Namba; Fabrizio Lombardi (IEEE Trans. Computers, 2018)

On Coding for Endurance Enhancement and Error Control of Phase Change Memories With Write Latency Reduction. - Kazuteru Namba; Fabrizio Lombardi (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Low Redundancy Double Error Correction Spotty Codes Combined with Gray Coding for 64 Data Bits Memories of 4-bit Multilevel Cells. - Shanshan Liu 001; Pedro Reviriego; Kazuteru Namba; Salvatore Pontarelli; Liyi Xiao; Fabrizio Lombardi (DFT, 2019)

Coding for Write Latency Reduction in a Multi-Level Cell (MLC) Phase Change Memory (PCM). - Kazuteru Namba; Fabrizio Lombardi (IEEE Trans. Computers, 2019)

Influence of Recognition Performance on Recurrent Neural Network Using Phase-Change Memory as Synapses. - Tomohiro Takahashi; Kazuteru Namba (ICCE-TW, 2020)

Master-Slave FF Using DICE Capable of Tolerating Soft Errors Occurring Around Clock Edge. - Kazuteru Namba (IEICE Trans. Inf. Syst., 2020)

Complete Double Node Upset Tolerant Latch Using C-Element. - Yuta Yamamoto; Kazuteru Namba (IEICE Trans. Inf. Syst., 2020)

Relaxing device requirements for non-linearity in Deep Neural Networks accelerators with Phase Change Memory. - Keisuke Kozu; Kazuteru Namba (ICCE-TW, 2021)

A Double Node Upset tolerant SR latch using C-element. - Shogo Takahashi; Kazuteru Namba (ICCE-TW, 2022)

Stuck-at Fault Tolerance in DNN Using Statistical data. - Tomohiro Ishii; Kazuteru Namba (PRDC, 2022)

Low Power Neural Network by Reducing SRAM Operating Voltage. - Keisuke Kozu; Yuya Tanabe; Masato Kitakami; Kazuteru Namba (IEEE Access, 2022)

SRAM-based efficiency memory model for quantized convolutional neural networks. - Ji Wu; Kazuteru Namba (ICCE-Taiwan, 2023)

Board design of digital chirp generator for earth observation. - Yoshiaki Saito; Kazuteru Namba; Josaphat Tetuko Sri Sumantyo (ICCE-Taiwan, 2024)

A Master-Slave Flip-Flop with Double-Node-Upset Self-Recovery and Soft Error Tolerance around Clock Edges. - Song Wang; Kazuteru Namba (ICCE-Taiwan, 2024)

Effect of RESET operation of CiM with PCM on recognition accuracy. - Kento Yano; You Yin; Kazuteru Namba (ICCE-Taiwan, 2024)

FPGA Cluster Based System with Adaptive TMR/DMR for Soft Error Mitigation. - Homu Omura; Kazuteru Namba (PRDC, 2024)

6T-8T Hybrid SRAM for Lower-Power Neural-Network Processing by Lowering Operating Voltage. - Ji Wu; Ruoxi Yu; Kazuteru Namba (IEICE Trans. Inf. Syst., 2024)