Accelerating deep learning by binarized hardware. - Shinya Takamaeda-Yamazaki; Kodai Ueyoshi; Kota Ando; Ryota Uematsu; Kazutoshi Hirose; Masayuki Ikebe; Tetsuya Asai; Masato Motomura (APSIPA, 2017)

Logarithmic Compression for Memory Footprint Reduction in Neural Network Training. - Kazutoshi Hirose; Ryota Uematsu; Kota Ando; Kentaro Orimo; Kodai Ueyoshi; Masayuki Ikebe; Tetsuya Asai; Shinya Takamaeda-Yamazaki; Masato Motomura (CANDAR, 2017)

In-memory area-efficient signal streaming processor design for binary neural networks. - Haruyoshi Yonekawa; Shimpei Sato; Hiroki Nakahara; Kota Ando; Kodai Ueyoshi; Kazutoshi Hirose; Kentaro Orimo; Shinya Takamaeda-Yamazaki; Masayuki Ikebe; Tetsuya Asai; Masato Motomura (MWSCAS, 2017)

Quantization Error-Based Regularization in Neural Networks. - Kazutoshi Hirose; Kota Ando; Kodai Ueyoshi; Masayuki Ikebe; Tetsuya Asai; Masato Motomura; Shinya Takamaeda-Yamazaki (SGAI Conf., 2017)

Dither NN: An Accurate Neural Network with Dithering for Low Bit-Precision Hardware. - Kota Ando; Kodai Ueyoshi; Yuka Oba; Kazutoshi Hirose; Ryota Uematsu; Takumi Kudo; Masayuki Ikebe; Tetsuya Asai; Shinya Takamaeda-Yamazaki; Masato Motomura (FPT, 2018)

QUEST: A 7.49TOPS multi-purpose log-quantized DNN inference engine stacked on 96MB 3D SRAM using inductive-coupling technology in 40nm CMOS. - Kodai Ueyoshi; Kota Ando; Kazutoshi Hirose; Shinya Takamaeda-Yamazaki; Junichiro Kadomoto; Tomoki Miyata; Mototsugu Hamada; Tadahiro Kuroda; Masato Motomura (ISSCC, 2018)

Area and Energy Optimization for Bit-Serial Log-Quantized DNN Accelerator with Shared Accumulators. - Takumi Kudo; Kodai Ueyoshi; Kota Ando; Kazutoshi Hirose; Ryota Uematsu; Yuka Oba; Masayuki Ikebe; Tetsuya Asai; Masato Motomura; Shinya Takamaeda-Yamazaki (MCSoC, 2018)

Dither NN: Hardware/Algorithm Co-Design for Accurate Quantized Neural Networks. - Kota Ando; Kodai Ueyoshi; Yuka Oba; Kazutoshi Hirose; Ryota Uematsu; Takumi Kudo; Masayuki Ikebe; Tetsuya Asai; Shinya Takamaeda-Yamazaki; Masato Motomura (IEICE Trans. Inf. Syst., 2019)

QUEST: Multi-Purpose Log-Quantized DNN Inference Engine Stacked on 96-MB 3-D SRAM Using Inductive Coupling Technology in 40-nm CMOS. - Kodai Ueyoshi; Kota Ando; Kazutoshi Hirose; Shinya Takamaeda-Yamazaki; Mototsugu Hamada; Tadahiro Kuroda; Masato Motomura (IEEE J. Solid State Circuits, 2019)

ProgressiveNN: Achieving Computational Scalability without Network Alteration by MSB-first Accumulative Computation. - Junnosuke Suzuki; Kota Ando; Kazutoshi Hirose; Kazushi Kawamura; Thiem Van Chu; Masato Motomura; Jaehoon Yu (CANDAR, 2020)

A 3D-Stacked SRAM using Inductive Coupling with Low-Voltage Transmitter and 12: 1 SerDes. - Kota Shiba; Tatsuo Omori; Kodai Ueyoshi; Kota Ando; Kazutoshi Hirose; Shinya Takamaeda-Yamazaki; Masato Motomura; Mototsugu Hamada; Tadahiro Kuroda (ISCAS, 2020)

Edge Inference Engine for Deep & Random Sparse Neural Networks with 4-bit Cartesian-Product MAC Array and Pipelined Activation Aligner. - Kota Ando; Jaehoon Yu; Kazutoshi Hirose; Hiroki Nakahara; Kazushi Kawamura; Thiem Van Chu; Masato Motomura (HCS, 2021)

Selective Fine-Tuning on a Classifier Ensemble: Realizing Adaptive Neural Networks With a Diversified Multi-Exit Architecture. - Kazutoshi Hirose; Shinya Takamaeda-Yamazaki; Jaehoon Yu; Masato Motomura (IEEE Access, 2021)

ProgressiveNN: Achieving Computational Scalability with Dynamic Bit-Precision Adjustment by MSB-first Accumulative Computation. - Junnosuke Suzuki; Tomohiro Kaneko; Kota Ando; Kazutoshi Hirose; Kazushi Kawamura; Thiem Van Chu; Masato Motomura; Jaehoon Yu (Int. J. Netw. Comput., 2021)

Multicoated Supermasks Enhance Hidden Networks. - Yasuyuki Okoshi; Ángel López García-Arias; Kazutoshi Hirose; Kota Ando; Kazushi Kawamura; Thiem Van Chu; Masato Motomura; Jaehoon Yu (ICML, 2022)

Hiddenite: 4K-PE Hidden Network Inference 4D-Tensor Engine Exploiting On-Chip Model Construction Achieving 34.8-to-16.0TOPS/W for CIFAR-100 and ImageNet. - Kazutoshi Hirose; Jaehoon Yu; Kota Ando; Yasuyuki Okoshi; Ángel López García-Arias; Junnosuke Suzuki; Thiem Van Chu; Kazushi Kawamura; Masato Motomura (ISSCC, 2022)