A functional memory type parallel processor for vector quantization. - Kazutoshi Kobayashi; Masayoshi Kinoshita; Masahiro Takeuchi; Hidetoshi Onodera; Keikichi Tamaru (ASP-DAC, 1997)

Real time low bit-rate video coding algorithm using multi-stage hierarchical vector quantization. - Kazuhiko Terada; Masahiro Takeuchi; Kazutoshi Kobayashi; Keikichi Tamaru (ICASSP, 1998)

A vector-pipeline DSP for low-rate videophones. - Kazutoshi Kobayashi; Makoto Eguchi; Takuya Iwahashi; Takehide Shibayama; Xiang Li; Kousuke Takai; Hidetoshi Onodera (ASP-DAC, 2001)

ST: PERL package for simulation and test environment. - Kazutoshi Kobayashi; Hidetoshi Onodera (ISCAS (5), 2001)

Measurement results of on-chip IR-drop. - Kazutoshi Kobayashi; Junji Yamaguchi; Hidetoshi Onodera (CICC, 2002)

An SoC architecture and its design methodology using unifunctional heterogeneous processor array. - Yoichi Yuyama; Masao Aramoto; Kazutoshi Kobayashi; Hidetoshi Onodera (ASP-DAC, 2004)

RTL/ISS co-modeling methodology for embedded processor using SystemC. - Yoichi Yuyama; Masao Aramoto; Kazutoshi Kobayashi; Hidetoshi Onodera (ISCAS (5), 2004)

A Comprehensive Simulation and Test Environment for Prototype VLSI Verification. - Kazutoshi Kobayashi; Hidetoshi Onodera (IEICE Trans. Inf. Syst., 2004)

A resource-shared VLIW processor architecture for area-efficient on-chip multiprocessing. - Kazutoshi Kobayashi; Masao Aramoto; Yoichi Yuyama; Akihiko Higuchi; Hidetoshi Onodera (ASP-DAC, 2005)

A yield and speed enhancement scheme under within-die variations on 90nm LUT array. - Kazuya Katsuki; Manabu Kotani; Kazutoshi Kobayashi; Hidetoshi Onodera (CICC, 2005)

A Resource-Shared VLIW Processor for Low-Power On-Chip Multiprocessing in the Nanometer Era. - Kazutoshi Kobayashi; Masao Aramoto; Hidetoshi Onodera (IEICE Trans. Electron., 2005)

Measurement results of within-die variations on a 90nm LUT array for speed and yield enhancement of reconfigurable devices. - Kazuya Katsuki; Manabu Kotani; Kazutoshi Kobayashi; Hidetoshi Onodera (ASP-DAC, 2006)

A Yield and Speed Enhancement Technique Using Reconfigurable Devices Against Within-Die Variations on the Nanometer Regime. - Kazutoshi Kobayashi; Manabu Kotani; Kazuya Katsuki; Y. Takatsukasa; K. Ogata; Yuuri Sugihara; Hidetoshi Onodera (FPL, 2006)

A Leakage Reduction Scheme for Sleep Transistors with Decoupling Capacitors in the Deep Submicron Era. - Kazutoshi Kobayashi; Akihiko Higuchi; Hidetoshi Onodera (IEICE Trans. Electron., 2006)

Alternate Self-Shielding for High-Speed and Reliable On-Chip Global Interconnect. - Yoichi Yuyama; Akira Tsuchiya; Kazutoshi Kobayashi; Hidetoshi Onodera (IEICE Trans. Electron., 2006)

A 90nm 8×16 FPGA Enhancing Speed and Yield Utilizing Within-Die Variations. - Yuuri Sugihara; Manabu Kotani; Kazuya Katsuki; Kazutoshi Kobayashi; Hidetoshi Onodera (ASP-DAC, 2007)

A 90 nm LUT Array for Speed and Yield Enhancement by Utilizing Within-Die Delay Variations. - Kazuya Katsuki; Manabu Kotani; Kazutoshi Kobayashi; Hidetoshi Onodera (IEICE Trans. Electron., 2007)

A 90 nm 48 x 48 LUT-Based FPGA Enhancing Speed and Yield Utilizing Within-Die Delay Variations. - Kazutoshi Kobayashi; Kazuya Katsuki; Manabu Kotani; Yuuri Sugihara; Yohei Kume; Hidetoshi Onodera (IEICE Trans. Electron., 2007)

Best ways to use billions of devices on a chip - Error predictive, defect tolerant and error recovery designs. - Kazutoshi Kobayashi; Hidetoshi Onodera (ASP-DAC, 2008)

Speed and yield enhancement by track swapping on critical paths utilizing random variations for FPGAs. - Yuuri Sugihara; Yohei Kume; Kazutoshi Kobayashi; Hidetoshi Onodera (FPGA, 2008)

A variation-aware constant-order optimization scheme utilizing delay detectors to search for fastest paths on FPGAS. - Kazutoshi Kobayashi; Yohei Kume; Cam Lai Ngo; Yuuri Sugihara; Hidetoshi Onodera (FPL, 2008)

Performance optimization by track swapping on critical paths utilizing random variations for FPGAS. - Yuuri Sugihara; Yohei Kume; Kazutoshi Kobayashi; Hidetoshi Onodera (FPL, 2008)

Erect of regularity-enhanced layout on printability and circuit performance of standard cells. - Hiroki Sunagawa; Haruhiko Terada; Akira Tsuchiya; Kazutoshi Kobayashi; Hidetoshi Onodera (ISQED, 2009)

Evaluation of FPGA design guardband caused by inhomogeneous NBTI degradation considering process variations. - Michitarou Yabuuchi; Kazutoshi Kobayashi (FPT, 2010)

A Stage-Level Recovery Scheme in Scalable Pipeline Modules for High Dependability. - Jun Yao 001; Hajime Shimada; Kazutoshi Kobayashi (IWIA, 2010)

A Minimal Roll-Back Based Recovery Scheme for Fault Toleration in Pipeline Processors. - Jun Yao 001; Ryoji Watanabe; Takashi Nakada; Hajime Shimada; Yasuhiko Nakashima; Kazutoshi Kobayashi (PRDC, 2010)

An Area/Delay Efficient Dual-Modular Flip-Flop with Higher SEU/SET Immunity. - Jun Furuta; Kazutoshi Kobayashi; Hidetoshi Onodera (IEICE Trans. Electron., 2010)

Effect of Regularity-Enhanced Layout on Variability and Circuit Performance of Standard Cells. - Hiroki Sunagawa; Haruhiko Terada; Akira Tsuchiya; Kazutoshi Kobayashi; Hidetoshi Onodera (IPSJ Trans. Syst. LSI Des. Methodol., 2010)

A 65nm flip-flop array to measure soft error resiliency against high-energy neutron and alpha particles. - Jun Furuta; Chikara Hamanaka; Kazutoshi Kobayashi; Hidetoshi Onodera (ASP-DAC, 2011)

Correlations between well potential and SEUs measured by well-potential perturbation detectors in 65nm. - Jun Furuta; Ryosuke Yamamoto; Kazutoshi Kobayashi; Hidetoshi Onodera (A-SSCC, 2011)

Modeling of Random Telegraph Noise under circuit operation - Simulation and measurement of RTN-induced delay fluctuation. - Kyosuke Ito; Takashi Matsumoto; Shinichi Nishizawa; Hiroki Sunagawa; Kazutoshi Kobayashi; Hidetoshi Onodera (ISQED, 2011)

Variation-Tolerance of a 65-nm Error-Hardened Dual-Modular-Redundancy Flip-Flop Measured by Shift-Register-Based Monitor Structures. - Chikara Hamanaka; Ryosuke Yamamoto; Jun Furuta; Kanto Kubota; Kazutoshi Kobayashi; Hidetoshi Onodera (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011)

NBTI-Induced Delay Degradation Analysis of FPGA Routing Structures. - Michitarou Yabuuchi; Kazutoshi Kobayashi (IPSJ Trans. Syst. LSI Des. Methodol., 2012)

A Radiation-Hard Redundant Flip-Flop to Suppress Multiple Cell Upset by Utilizing the Parasitic Bipolar Effect. - Kuiyuan Zhang; Jun Furuta; Ryosuke Yamamoto; Kazutoshi Kobayashi; Hidetoshi Onodera (IEICE Trans. Electron., 2013)

Impact of random telegraph noise on CMOS logic circuit reliability. - Takashi Matsumoto; Kazutoshi Kobayashi; Hidetoshi Onodera (CICC, 2014)

A Perpetuum Mobile 32bit CPU with 13.4pJ/cycle, 0.14µA sleep current using Reverse Body Bias Assisted 65nm SOTB CMOS technology. - Koichiro Ishibashi; Nobuyuki Sugii; Kimiyoshi Usami; Hideharu Amano; Kazutoshi Kobayashi; Cong-Kha Pham; Hideki Makiyama; Yoshiki Yamamoto; Hirofumi Shinohara; Toshiaki Iwamatsu; Yasuo Yamaguchi; Hidekazu Oda; et al. (COOL Chips, 2014)

Foreword. - Kazutoshi Kobayashi (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014)

Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-Based Design and Its Irradiation Testing. - Hiroaki Konoura; Dawood Alnajiar; Yukio Mitsuyama; Hajime Shimada; Kazutoshi Kobayashi; Hiroyuki Kanbara; Hiroyuki Ochi; Takashi Imagawa; Kazutoshi Wakabayashi; Masanori Hashimoto; Takao Onoye; Hidetoshi Onodera (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014)

Correlations between BTI-Induced Degradations and Process Variations on ASICs and FPGAs. - Michitarou Yabuuchi; Ryo Kishida; Kazutoshi Kobayashi (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014)

Reliability-configurable mixed-grained reconfigurable array compatible with high-level synthesis. - Masanori Hashimoto; Dawood Alnajiar; Hiroaki Konoura; Yukio Mitsuyama; Hajime Shimada; Kazutoshi Kobayashi; Hiroyuki Kanbara; Hiroyuki Ochi; Takashi Imagawa; Kazutoshi Wakabayashi; Takao Onoye; Hidetoshi Onodera (ASP-DAC, 2015)

Impact of random telegraph noise on ring oscillators evaluated by circuit-level simulations. - Azusa Oshima; Pieter Weckx; Ben Kaczer; Kazutoshi Kobayashi; Takashi Matsumoto (ICICDT, 2015)

Negative bias temperature instability caused by plasma induced damage in 65 nm bulk and Silicon on thin BOX (SOTB) processes. - Ryo Kishida; Azusa Oshima; Kazutoshi Kobayashi (IRPS, 2015)

Impact of Cell Distance and Well-contact Density on Neutron-induced Multiple Cell Upsets. - Jun Furuta; Kazutoshi Kobayashi; Hidetoshi Onodera (IEICE Trans. Electron., 2015)

A Perpetuum Mobile 32bit CPU on 65nm SOTB CMOS Technology with Reverse-Body-Bias Assisted Sleep Mode. - Koichiro Ishibashi; Nobuyuki Sugii; Shiro Kamohara; Kimiyoshi Usami; Hideharu Amano; Kazutoshi Kobayashi; Cong-Kha Pham (IEICE Trans. Electron., 2015)

Size Optimization Technique for Logic Circuits that Considers BTI and Process Variations. - Michitarou Yabuuchi; Kazutoshi Kobayashi (IPSJ Trans. Syst. LSI Des. Methodol., 2016)

Highly-reliable integrated circuits for Gro. - Kazutoshi Kobayashi (ASICON, 2017)

Circuit-level simulation methodology for Random Telegraph Noise by using Verilog-AMS. - Takuya Komawaki; Michitarou Yabuuchi; Ryo Kishida; Jun Furuta; Takashi Matsumoto; Kazutoshi Kobayashi (ICICDT, 2017)

Replication of Random Telegraph Noise by Using a Physical-Based Verilog-AMS Model. - Takuya Komawaki; Michitarou Yabuuchi; Ryo Kishida; Jun Furuta; Takashi Matsumoto; Kazutoshi Kobayashi (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017)

Sensitivity to soft errors of NMOS and PMOS transistors evaluated by latches with stacking structures in a 65 nm FDSOI process. - Kodai Yamada; Haruki Maruoka; Jun Furuta; Kazutoshi Kobayashi (IRPS, 2018)

A Low-Power Radiation-Hardened Flip-Flop with Stacked Transistors in a 65 nm FDSOI Process. - Haruki Maruoka; Masashi Hifumi; Jun Furuta; Kazutoshi Kobayashi (IEICE Trans. Electron., 2018)

Temperature Dependence of Bias Temperature Instability (BTI) in Long-term Measurement by BTI-sensitive and -insensitive Ring Oscillators Removing Environmental Fluctuation. - Takuya Asuke; Ryo Kishida; Jun Furuta; Kazutoshi Kobayashi (ASICON, 2019)

Soft-Error Tolerance Depending on Supply Voltage by Heavy Ions on Radiation-Hardened Flip Flops in a 65 nm Bulk Process. - Yuto Tsukita; Mitsunori Ebara; Jun Furuta; Kazutoshi Kobayashi (ASICON, 2019)

Monolithically integrated GaN power ICs designed using the MIT virtual source GaNFET (MVSG) compact model for enhancement-mode p-GaN gate power HEMTs, logic transistors and resistors. - Shuzhen You; Xiangdong Li; Stefaan Decoutere; Guido Groeseneken; Zhanfei Chen; Jun Liu; Yuki Yamashita; Kazutoshi Kobayashi (ESSDERC, 2019)

Comparison of Radiation Hardness of Stacked Transmission-Gate Flip Flop and Stacked Tristate-Inverter Flip Flop in a 65 nm Thin BOX FDSOI Process. - Mitsunori Ebara; Kodai Yamada; Jun Furuta; Kazutoshi Kobayashi (IOLTS, 2019)

Compact Modeling of NBTI Replicating AC Stress / Recovery from a Single-shot Long-term DC Measurement. - Takumi Hosaka; Shinichi Nishizawa; Ryo Kishida; Takashi Matsumoto; Kazutoshi Kobayashi (IOLTS, 2019)

Total Ionizing Dose Effects by alpha irradiation on circuit performance and SEU tolerance in thin BOX FDSOI process. - Takashi Yoshida; Kazutoshi Kobayashi; Jun Furuta (IOLTS, 2019)

Impact of Combinational Logic Delay for Single Event Upset on Flip Flops in a 65 nm FDSOI Process. - Jun Furuta; Yuto Tsukita; Kodai Yamada; Mitsunori Ebara; Kentaro Kojima; Kazutoshi Kobayashi (IRPS, 2019)

An Accurate Device-Level Simulation Method to Estimate Cross Sections of Single Event Upsets by Silicon Thickness in Raised Layer. - Kentaro Kojima; Kodai Yamada; Jun Furuta; Kazutoshi Kobayashi (IRPS, 2019)

Monolithic integration of gate driver and p-GaN power HEMT for MHz-switching implemented by e-mode GaN-on-SOI process. - Yuki Yamashita; Steve Stoffels; Niels Posthuma; Karen Geens; Xiangdong Li; Jun Furuta; Stefaan Decoutere; Kazutoshi Kobayashi (IEICE Electron. Express, 2019)

Characterizing SRAM and FF soft error rates with measurement and simulation. - Masanori Hashimoto; Kazutoshi Kobayashi; Jun Furuta; Shin-ichiro Abe; Yukinobu Watanabe (Integr., 2019)

Evaluation of Heavy-Ion-Induced Single Event Upset Cross Sections of a 65-nm Thin BOX FD-SOI Flip-Flops Composed of Stacked Inverters. - Kentaro Kojima; Kodai Yamada; Jun Furuta; Kazutoshi Kobayashi (IEICE Trans. Electron., 2020)

Universal NBTI Compact Model Replicating AC Stress/Recovery from a Single-shot Long-term DC Measurement. - Takumi Hosaka; Shinichi Nishizawa; Ryo Kishida; Takashi Matsumoto; Kazutoshi Kobayashi (IPSJ Trans. Syst. LSI Des. Methodol., 2020)

An Efficient and Accurate Time Step Control Method for Power Device Transient Simulation Utilizing Dominant Time Constant Approximation. - Shigetaka Kumashiro; Tatsuya Kamei; Akira Hiroki; Kazutoshi Kobayashi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Nonvolatile SRAM Using Fishbone-in-Cage Capacitor in a 180 nm Standard CMOS Process for Zero-Standby and Instant-Powerup Embedded Memory on IoT. - Takaki Urabe; Hiroyuki Ochi; Kazutoshi Kobayashi (COOL CHIPS, 2021)

Bias Temperature Instability Depending on Body Bias through Buried Oxide (BOX) Layer in a 65 nm Fully-Depleted Silicon-On-Insulator Process. - Ryo Kishida; Ikuo Suda; Kazutoshi Kobayashi (IRPS, 2021)

A Bit-Error Rate Measurement and Error Analysis of Wireline Data Transmission using Current Source Model for Single Event Effect under Irradiation Environment. - Takefumi Yoshikawa; Masahiro Ishimaru; Tatsuya Iwata; Fuma Mori; Kazutoshi Kobayashi (J. Electron. Test., 2021)

An E-mode p-GaN HEMT monolithically-integrated three-level gate driver operating with a single voltage supply. - Junichiro Nagao; Urmimala Chatterjee; Xiangdong Li; Jun Furuta; Stefaan Decoutere; Kazutoshi Kobayashi (IEICE Electron. Express, 2021)

An Analysis of Local BTI Variation with Ring-Oscillator in Advanced Processes and Its Impact on Logic Circuit and SRAM. - Mitsuhiko Igarashi; Yuuki Uchida; Yoshio Takazawa; Makoto Yabuuchi; Yasumasa Tsukamoto; Koji Shibutani; Kazutoshi Kobayashi (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2021)

Cost-Effective Test Screening Method on 40-nm Embedded SRAMs for Low-Power MCUs. - Yoshisato Yokoyama; Yuichiro Ishii; Koji Nii; Kazutoshi Kobayashi (IEEE Trans. Very Large Scale Integr. Syst., 2021)

Zero-standby-power Nonvolatile Standard Cell Memory Using FiCC for IoT Processors with Intermittent Operations. - Yuki Abe; Kazutoshi Kobayashi; Jun Shiomi; Hiroyuki Ochi (COOL CHIPS, 2022)

Radiation Hardened Flip-Flops Minimizing Area, Power, and Delay Overheads with 1/100 Lower α-SER in a 130 nm Bulk Process. - Ryuichi Nakajima; Kazuya Ioki; Jun Furuta; Kazutoshi Kobayashi (IOLTS, 2022)

An Aging Degradation Suppression Scheme at Constant Performance by Controlling Supply Voltage and Body Bias in a 65 nm Fully-Depleted Silicon-On-Insulator Process. - Ikuo Suda; Ryo Kishida; Kazutoshi Kobayashi (IRPS, 2022)

Nonvolatile Flip-Flops Using FiCC for IoT Processors with Intermittent Operations. - Yuki Abe; Kazutoshi Kobayashi; Hiroyuki Ochi (MWSCAS, 2022)

Ring Oscillators with identical Circuit Structure to Measure Bias Temperature Instability. - Daisuke Kikuta; Ryo Kishida; Kazutoshi Kobayashi (ASICON, 2023)

Scalable Highly Integrated Quantum Bit Error Correction System by Classical Electronics. - Kazutoshi Kobayashi (ASICON, 2023)

Frequency Dependency of Soft Error Rates Based on Dynamic Soft Error Measurements. - Haruto Sugisaki; Ryuichi Nakajima; Shotaro Sugitani; Jun Furuta; Kazutoshi Kobayashi (ICICDT, 2023)

SEU Sensitivity of PMOS and NMOS Transistors in a 65 nm Bulk Process by α-Particle Irradiation. - Keita Yoshida; Ryuichi Nakajima; Shotaro Sugitani; Takafumi Ito; Jun Furuta; Kazutoshi Kobayashi (ICICDT, 2023)

Radiation Hardness Evaluations of a Stacked Flip Flop in a 22 nm FD-SOI Process by Heavy-Ion Irradiation. - Shotaro Sugitani; Ryuichi Nakajima; Takafumi Ito; Jun Furuta; Kazutoshi Kobayashi; Mathieu Louvat; Francois Jacquet; Jean-Christophe Eloy; Olivier Montfort; Lionel Jure; Vincent Huard (IOLTS, 2023)

A 13-bit Radiation-Hardened SAR-ADC with Error Correction by Adaptive Topology Transformation. - Yuya Aoki; Tatsuya Iwata; Takuji Miki; Kazutoshi Kobayashi; Takefumi Yoshikawa (IRPS, 2023)

Ultra Long-term Measurement Results of BTI-induced Aging Degradation on 7-nm Ring Oscillators. - Kazutoshi Kobayashi; Tomoharu Kishita; Hiroki Nakano; Jun Furuta; Mitsuhiko Igarashi; Shigetaka Kumashiro; Michitarou Yabuuchi; Hironori Sakamoto (IRPS, 2023)

Radiation Hardened Flip-Flops with low Area, Delay and Power Overheads in a 65 nm bulk process. - Shotaro Sugitani; Ryuichi Nakajima; Keita Yoshida; Jun Furuta; Kazutoshi Kobayashi (IRPS, 2023)

Disturbance Aware Dynamic Power Reduction in Synchronous 2RW Dual-Port 8T SRAM by Self-Adjusting Wordline Pulse Timing. - Yoshisato Yokoyama; Koji Nii; Yuichiro Ishii; Shinji Tanaka; Kazutoshi Kobayashi (IEEE J. Solid State Circuits, 2023)

Nonvolatile Storage Cells Using FiCC for IoT Processors with Intermittent Operations. - Yuki Abe; Kazutoshi Kobayashi; Jun Shiomi; Hiroyuki Ochi (IEICE Trans. Electron., 2023)

A Partially-redundant Flip-flip Suitable for Mitigating Single Event Upsets in a FD-SOI Process with Low Performance Overhead. - Jun Furuta; Shotaro Sugitani; Ryuichi Nakajima; Kazutoshi Kobayashi (IRPS, 2024)

An Approach to Neutron-Induced SER Evaluation Using a Clinical 290 MeV/ u Carbon Beam and Particle Transport Simulations. - Ryuichi Nakajima; Shotaro Sugitani; Haruto Sugisaki; Takafumi Ito; Jun Furuta; Kazutoshi Kobayashi; Makoto Sakai (IRPS, 2024)

A Power Reduction Scheme by Arithmetic Format Conversion for a DSP to Estimate Qubit States Under 4K Cryogenic Environment. - Takashi Imagawa; Ryo Kishida; Yuki Koyama 005; Kazutoshi Kobayashi; Takefumi Miyoshi (QCE, 2024)

Frequency dependence of soft error rates induced by alpha-particle and heavy ion. - Haruto Sugisaki; Ryuichi Nakajima; Shotaro Sugitani; Jun Furuta; Kazutoshi Kobayashi (IEICE Electron. Express, 2024)

Measuring SET Pulse Widths in pMOSFETs and nMOSFETs Separately by Heavy Ion and Neutron Irradiation. - Jun Furuta; Shotaro Sugitani; Ryuichi Nakajima; Takafumi Ito; Kazutoshi Kobayashi (IEICE Trans. Electron., 2024)

Soft-Error Tolerance by Guard-Gate Structures on Flip-Flops in 22 and 65 nm FD-SOI Technologies. - Ryuichi Nakajima; Takafumi Ito; Shotaro Sugitani; Tomoya Kii; Mitsunori Ebara; Jun Furuta; Kazutoshi Kobayashi; Mathieu Louvat; Francois Jacquet; Jean-Christophe Eloy; Olivier Montfort; Lionel Jure; et al. (IEICE Trans. Electron., 2024)

Physics-based Modeling to Extend a MOSFET Compact Model for Cryogenic Operation. - Dondee Navarro; Shin Taniguchi; Chika Tanaka; Kazutoshi Kobayashi; Takashi Sato 001; Michihiro Shintani (ASP-DAC, 2025)

Panel Discussions: "Sustainable AI: Emerging Architectures, Devices, and Quantum Computing Towards Future Computing". - Tohru Ishihara; Jangwoo Kim; Kazutoshi Kobayashi; Jose Martinez (COOL CHIPS, 2025)

Comparative Analysis of TID Effects in a 65 nm FD-SOI Process Under Gamma-Ray and Alpha-Ray Irradiation. - Hikaru Nakamoto; Taiki Ozawa; Ryuichi Nakajima; Haruto Sugisaki; Keita Yoshida; Jun Furuta; Kazutoshi Kobayashi (IOLTS, 2025)

Investigation of the Time-Dependent BTI-induced Degradation Distribution for Ring Oscillators in Ultra-Long-Term Stress Conditions. - Tomoharu Kishita; Ryo Kishida; Kazutoshi Kobayashi (IRPS, 2025)

A 22-nm Surface Code Decoder Using Greedy Algorithm. - Junichiro Kadomoto; Ren Aoyama; Kazutoshi Kobayashi (ISCAS, 2025)

Radiation-Hardened Flip-Flops in a 65 nm Bulk Process for Terrestrial Applications Coping with Radiation Hardness and Performance Overheads. - Shotaro Sugitani; Ryuichi Nakajima; Keita Yoshida; Jun Furuta; Kazutoshi Kobayashi (IEICE Trans. Electron., 2025)