A half-pel precision MPEG2 motion-estimation processor with concurrent three-vector search. - Kazuya Ishihara; Shinichi Masuda; Shin-ichi Hattori; Hirofumi Nishikawa; Yoshihide Ajioka; Tsuyoshi Yamada; Hiroyuki Amishiro; Shin-ichi Uramoto; Masahiko Yoshimoto; Tadashi Sumi (IEEE J. Solid State Circuits, 1995)

A 165-GOPS motion estimation processor with adaptive dual-array architecture for high quality video-encoding applications. - Atsuo Hanami; Stefan Scotzniovsky; Kazuya Ishihara; Tetsuya Matsumura; Shin'ichi Takeuchi; Haruyuki Ohkuma; Koji Nishigaki; Hirokazu Suzuki; Masahiro Kazayama; Toyohiko Yoshida; Koji Tsuchihashi (CICC, 1998)

A 99-mm2, 0.7-W, single-chip MPEG-2 422P@ML video, audio, and system encoder with a 64-Mbit embedded DRAM for portable 422P@HL encoder system. - Satoshi Kumaki; Hidehiro Takata; Yoshihide Ajioka; Tsukasa Ooishi; Kazuya Ishihara; Atsuo Hanami; Takaharu Tsuji; Yusuke Kanehira; Tetsuya Watanabe; Chikayoshi Morishima; Tomoaki Yoshizawa; Hidenori Sato; et al. (CICC, 2001)

A 99-mm2 0.7-W single-chip MPEG-2 422P@ML video, audio, and system encoder with a 64-Mb embedded DRAM for portable 422P@HL encoder system. - Satoshi Kumaki; Hidehiro Takata; Yoshihide Ajioka; Tsukasa Ooishi; Kazuya Ishihara; Atsuo Hanami; Takaharu Tsuji; Tetsuya Watanabe; Chikayoshi Morishima; Tomoaki Yoshizawa; Hidenori Sato; Shin-ichi Hattori; et al. (IEEE J. Solid State Circuits, 2002)

Dependable SRAM with enhanced read-/write-margins by fine-grained assist bias control for low-voltage operation. - Koji Nii; Makoto Yabuuchi; Hidehiro Fujiwara; Hirofumi Nakano; Kazuya Ishihara; Hiroyuki Kawai; Kazutami Arimoto (SoCC, 2010)