One chip demodulator using RF front-end SAW correlator for 2.4 GHz asynchronous spread spectrum modem. - Hiroyuki Nakase; T. Kasai; Y. Nakamura; Kazuya Masu; Kazuo Tsubouchi (PIMRC, 1994)

Design and implementation of intracell reverse link using approximately synchronized CDMA. - Suguru Kameda; Kouichi Takahashi; Taketo Kamata; Jae Sang Cha; Hiroyuki Nakase; Kazuya Masu; Kazuo Tsubouchi (PIMRC, 2000)

Implementation of low power matched filter LSI for IMT-2000. - Hiroyuki Nakase; Koji Kubota; Suguru Kameda; Kenji Togura; Kazuya Masu; Kazuo Tsubouchi (PIMRC, 2000)

Differential transmission line interconnect for high speed and low power global wiring. - Shinichiro Gomi; Kohichi Nakamura; Hiroyuki Ito; Kenichi Okada 001; Kazuya Masu (CICC, 2004)

ULSI Interconnect Length Distribution Model Considering Core Utilization. - Hidenari Nakashima; Junpei Inoue; Kenichi Okada 001; Kazuya Masu (DATE, 2004)

High speed and low power on-chip micro network circuit with differential transmission line. - Shinichiro Gomi; Kohichi Nakamura; Hiroyuki Ito; Hideyuki Sugita; Kenichi Okada 001; Kazuya Masu (SoC, 2004)

Inductance-Tuned LC-VCO for Reconfigurable RF Circuit Design. - Yoshiaki Yoshihara; Hirotaka Sugawara; Hiroyuki Ito; Kenichi Okada 001; Kazuya Masu (IEICE Electron. Express, 2004)

Evaluation of on-chip transmission line interconnect using wire length distribution. - Junpei Inoue; Hiroyuki Ito; Shinichiro Gomi; Takanori Kyogoku; Takumi Uezono; Kenichi Okada 001; Kazuya Masu (ASP-DAC, 2005)

A dynamic reconfigurable RF circuit architecture. - Kenichi Okada 001; Yoshiaki Yoshihara; Hirotaka Sugawara; Kazuya Masu (ASP-DAC, 2005)

Wire Length Distribution Model Considering Core Utilization for System on Chip. - Takanori Kyogoku; Junpei Inoue; Hidenari Nakashima; Takumi Uezono; Kenichi Okada 001; Kazuya Masu (ISVLSI, 2005)

Prediction of delay time for future LSI using on-chip transmission line interconnects. - Takumi Uezono; Junpei Inoue; Takanori Kyogoku; Kenichi Okada 001; Kazuya Masu (SLIP, 2005)

Wire Length Distribution Model for System LSI. - Takanori Kyogoku; Junpei Inoue; Hidenari Nakashima; Takumi Uezono; Kenichi Okada 001; Kazuya Masu (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005)

Circuit Performance Prediction Considering Core Utilization with Interconnect Length Distribution Model. - Hidenari Nakashima; Junpei Inoue; Kenichi Okada 001; Kazuya Masu (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005)

Evaluation of X Architecture Using Interconnect Length Distribution. - Hidenari Nakashima; Naohiro Takagi; Junpei Inoue; Kenichi Okada 001; Kazuya Masu (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005)

Wide Tuning Range LC-VCO Using Variable Inductor for Reconfigurable RF Circuit. - Yoshiaki Yoshihara; Hirotaka Sugawara; Hiroyuki Ito; Kenichi Okada 001; Kazuya Masu (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005)

Reconfigurable CMOS low noise amplifier for self compensation. - D. Kawazoe; Hirotaka Sugawara; Tatsuya Ito; Kenichi Okada 001; Kazuya Masu (ISCAS, 2006)

Via Distribution Model for Yield Estimation. - Takumi Uezono; Kenichi Okada 001; Kazuya Masu (ISQED, 2006)

Estimation of Power Reduction by On-Chip Transmission Line for 45nm Technology. - Kenichi Okada 001; Takumi Uezono; Kazuya Masu (PATMOS, 2006)

RF Passive Components Using Metal Line on Si CMOS. - Kazuya Masu; Kenichi Okada 001; Hiroyuki Ito (IEICE Trans. Electron., 2006)

Statistical Modeling of a Via Distribution for Yield Estimation. - Takumi Uezono; Kenichi Okada 001; Kazuya Masu (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006)

Reconfigurable CMOS Low Noise Amplifier Using Variable Bias Circuit for Self Compensation. - Satoshi Fukuda; D. Kawazoe; Kenichi Okada 001; Kazuya Masu (ASP-DAC, 2007)

A Wideband CMOS LC-VCO Using Variable Inductor. - Kazuma Ohashi; Yusaku Ito; Yoshiaki Yoshihara; Kenichi Okada 001; Kazuya Masu (ASP-DAC, 2007)

A Multi-Drop Transmission-Line Interconnect in Si LSI. - Junki Seita; Hiroyuki Ito; Kenichi Okada 001; Takashi Sato 001; Kazuya Masu (ASP-DAC, 2007)

Improvement of power distribution network using correlation-based regression analysis. - Shiho Hagiwara; Takumi Uezono; Takashi Sato 001; Kazuya Masu (ACM Great Lakes Symposium on VLSI, 2007)

A MOS Transistor-Array for Accurate Measurement of Subthreshold Leakage Variation. - Takashi Sato 001; Takumi Uezono; Shiho Hagiwara; Kenichi Okada 001; Shuhei Amakawa; Noriaki Nakayama; Kazuya Masu (ISQED, 2007)

Weakness Identification for Effective Repair of Power Distribution Network. - Takashi Sato 001; Shiho Hagiwara; Takumi Uezono; Kazuya Masu (PATMOS, 2007)

Adaptable wire-length distribution with tunable occupation probability. - Shuhei Amakawa; Takumi Uezono; Takashi Sato 001; Kenichi Okada 001; Kazuya Masu (SLIP, 2007)

Low-Loss Distributed Constant Passive Devices Using Wafer-Level Chip Scale Package Technology. - Hiroyuki Ito; Hideyuki Sugita; Kenichi Okada; Tatsuya Ito; Kazuhisa Itoi; Masakazu Sato; Ryozo Yamauchi; Kazuya Masu (IEICE Trans. Electron., 2007)

LVDS-type on-chip transmision line interconnect with passive equalizers in 90nm CMOS process. - Akiko Mineyama; Hiroyuki Ito; Takahiro Ishii; Kenichi Okada 001; Kazuya Masu (ASP-DAC, 2008)

Small-area CMOS RF distributed mixer using multi-port inductors. - Susumu Sadoshima; Satoshi Fukuda; Tackya Yammouch; Hiroyuki Ito; Kenichi Okada 001; Kazuya Masu (ASP-DAC, 2008)

Determination of optimal polynomial regression function to decompose on-die systematic and random variations. - Takashi Sato 001; Hiroyuki Ueyama; Noriaki Nakayama; Kazuya Masu (ASP-DAC, 2008)

Non-parametric statistical static timing analysis: an SSTA framework for arbitrary distribution. - Masanori Imai; Takashi Sato 001; Noriaki Nakayama; Kazuya Masu (DAC, 2008)

A 1.7-GHz 1.5-mW digitally-controlled FBAR oscillator with 0.03-ppb resolution. - Hiroyuki Ito; Hasnain Lakdawala; Ashoke Ravi; Stefano Pellerano; Rick Ruby; Krishnamurthy Soumyanath; Kazuya Masu (ESSCIRC, 2008)

An 8Gbps 2.5mW on-chip pulsed-current-mode transmission line interconnect with a stacked-switch Tx. - Tomoaki Maekawa; Hiroyuki Ito; Kazuya Masu (ESSCIRC, 2008)

Application of Correlation-Based Regression Analysis for Improvement of Power Distribution Network. - Shiho Hagiwara; Takumi Uezono; Takashi Sato 001; Kazuya Masu (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)

An Evaluation Method of the Number of Monte Carlo STA Trials for Statistical Path Delay Analysis. - Masanori Imai; Takashi Sato 001; Noriaki Nakayama; Kazuya Masu (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)

Reconfigurable RF CMOS Circuit for Cognitive Radio. - Kazuya Masu; Kenichi Okada 001 (IEICE Trans. Commun., 2008)

Layout-Aware Compact Model of MOSFET Characteristics Variations Induced by STI Stress. - Kenta Yamada; Takashi Sato 001; Shuhei Amakawa; Noriaki Nakayama; Kazuya Masu; Shigetaka Kumashiro (IEICE Trans. Electron., 2008)

A Bidirectional- and Multi-Drop-Transmission-Line Interconnect for Multipoint-to-Multipoint On-Chip Communications. - Hiroyuki Ito; Makoto Kimura; Kazuya Miyashita; Takahiro Ishii; Kenichi Okada 001; Kazuya Masu (IEEE J. Solid State Circuits, 2008)

Physical Modeling of MEMS Variable Inductor. - Tackya Yammouch; Kenichi Okada 001; Kazuya Masu (IEEE Trans. Circuits Syst. II Express Briefs, 2008)

An Adaptive Test for Parametric Faults Based on Statistical Timing Information. - Michihiro Shintani; Takumi Uezono; Tomoyuki Takahashi; Hiroyuki Ueyama; Takashi Sato 001; Kazumi Hatayama; Takashi Aikyo; Kazuya Masu (Asian Test Symposium, 2009)

Design of CMOS inverter-based output buffers adapting the cherry-hooper broadbanding technique. - Tomoaki Maekawa; Shuhei Amakawa; Noboru Ishihara; Kazuya Masu (ECCTD, 2009)

A low-phase-noise injection-locked differential ring-VCO with half-integral subharmonic locking in 0.18 µm CMOS. - Yuka Kobayashi; Shuhei Amakawa; Noboru Ishihara; Kazuya Masu (ESSCIRC, 2009)

Physical design challenges to nano-CMOS circuits. - Kazuya Masu; Noboru Ishihara; Noriaki Nakayama; Takashi Sato 001; Shuhei Amakawa (IEICE Electron. Express, 2009)

Analytical Estimation of Path-Delay Variation for Multi-Threshold CMOS Circuits. - Shiho Hagiwara; Takashi Sato 001; Kazuya Masu (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

Tunable CMOS LNA Using a Variable Inductor for a Reconfigurable RF Circuit. - Hirotaka Sugawara; Kenichi Okada 001; Kazuya Masu (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

One-Shot Voltage-Measurement Circuit Utilizing Process Variation. - Takumi Uezono; Takashi Sato 001; Kazuya Masu (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

2-Port Modeling Technique for Surface-Mount Passive Components Using Partial Inductance Concept. - Koh Yamanaga; Takashi Sato 001; Kazuya Masu (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

Accurate Array-Based Measurement for Subthreshold-Current of MOS Transistors. - Takashi Sato 001; Hiroyuki Ueyama; Noriaki Nakayama; Kazuya Masu (IEEE J. Solid State Circuits, 2009)

Characterization of On-Chip Multiport Inductors for Small-Area RF Circuits. - Takeshi Ito; Kenichi Okada 001; Kazuya Masu (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

Decomposition of drain-current variation into gain-factor and threshold voltage variations. - Takashi Sato 001; Takumi Uezono; Noriaki Nakayama; Kazuya Masu (ISCAS, 2010)

Scan based process parameter estimation through path-delay inequalities. - Takumi Uezono; Tomoyuki Takahashi; Michihiro Shintani; Kazumi Hatayama; Kazuya Masu; Hiroyuki Ochi; Takashi Sato 001 (ISCAS, 2010)

Robust importance sampling for efficient SRAM yield analysis. - Takanori Date; Shiho Hagiwara; Kazuya Masu; Takashi Sato 001 (ISQED, 2010)

Linear time calculation of state-dependent power distribution network capacitance. - Shiho Hagiwara; Koh Yamanaga; Ryo Takahashi; Kazuya Masu; Takashi Sato 001 (ISQED, 2010)

Application of generalized scattering matrix for prediction of power supply noise. - Koh Yamanaga; Kazuya Masu; Takashi Sato 001 (SLIP, 2010)

Path clustering for adaptive test. - Takumi Uezono; Tomoyuki Takahashi; Michihiro Shintani; Kazumi Hatayama; Kazuya Masu; Hiroyuki Ochi; Takashi Sato 001 (VTS, 2010)

Wide-band, high linear low noise amplifier design in 0.18um CMOS technology. - Mousa M. Othman; Shuhei Amakawa; Noboru Ishihara; Kazuya Masu (IEICE Electron. Express, 2010)

A study for the efficiency of transmission energy for different high-frequency communication circuits. - Toshiyuki Umeda; Kazuya Masu (IEICE Electron. Express, 2010)

Linear Time Calculation of On-Chip Power Distribution Network Capacitance Considering State-Dependence. - Shiho Hagiwara; Koh Yamanaga; Ryo Takahashi; Kazuya Masu; Takashi Sato 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010)

A Time-Slicing Ring Oscillator for Capturing Time-Dependent Delay Degradation and Power Supply Voltage Fluctuation. - Takumi Uezono; Kazuya Masu; Takashi Sato 001 (IEICE Trans. Electron., 2010)

A Universal Equivalent Circuit Model for Ceramic Capacitors. - Koh Yamanaga; Shuhei Amakawa; Kazuya Masu; Takashi Sato 001 (IEICE Trans. Electron., 2010)

A ring-VCO-based injection-locked frequency multiplier using a new pulse generation technique in 65 nm CMOS. - Norifumi Kanemaru; Sho Ikeda; Tatsuya Kamimura; Sang-yeop Lee; Satoru Tanoi; Hiroyuki Ito; Noboru Ishihara; Kazuya Masu (ISOCC, 2011)

A 21 V output charge pump circuit with appropriate well-bias supply technique in 0.18 μm Si CMOS. - Atsushi Shirane; Hiroyuki Ito; Noboru Ishihara; Kazuya Masu (ISOCC, 2011)

RF CMOS Integrated Circuit: History, Current Status and Future Prospects. - Noboru Ishihara; Shuhei Amakawa; Kazuya Masu (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011)

A Tunable Wideband Frequency Synthesizer Using LC-VCO and Mixer for Reconfigurable Radio Transceivers. - Yusaku Ito; Kenichi Okada 001; Kazuya Masu (J. Electr. Comput. Eng., 2011)

Optimal design method for chip-area-efficient CMOS low-dropout regulator. - Sho Ikeda; Hiroyuki Ito; Noboru Ishihara; Kazuya Masu (APCCAS, 2012)

Injection-locked fractional frequency multiplier with automatic reference pulse-selection technique. - Sang-yeop Lee; Hiroyuki Ito; Satoru Tanoi; Noboru Ishihara; Kazuya Masu (IEICE Electron. Express, 2012)

RF signal generator using time domain harmonic suppression technique in 90nm CMOS. - Kazuo Nakano; Shuhei Amakawa; Noboru Ishihara; Kazuya Masu (IEICE Electron. Express, 2012)

A Ring-VCO-Based Injection-Locked Frequency Multiplier with Novel Pulse Generation Technique in 65 nm CMOS. - Sang-yeop Lee; Norifumi Kanemaru; Sho Ikeda; Tatsuya Kamimura; Satoru Tanoi; Hiroyuki Ito; Noboru Ishihara; Kazuya Masu (IEICE Trans. Electron., 2012)

Challenges in integration of diverse functionalities on CMOS. - Kazuya Masu; Noboru Ishihara; Toshifumi Konishi; Katsuyuki Machida; Hiroshi Toshiyoshi (ASP-DAC, 2013)

A mixed-design technique for integrated MEMS using a circuit simulator with HDL. - Hiroshi Toshiyoshi; Toshifumi Konishi; Katsuyuki Machida; Kazuya Masu (MIXDES, 2013)

A process-scalable RF transmitter using 90nm and 65nm Si CMOS. - Atsushi Shirane; Hiroyuki Ito; Noboru Ishihara; Kazuya Masu (VLSI-DAT, 2013)

A 60GHz 3-dB tandem coupler using offset broadside-coupled lines on a silicon substrate. - Hamid Kiumarsi; Hiroyuki Ito; Kenichi Okada 001; Yusuke Uemichi; Yasuto Chiba; Noboru Ishihara; Kazuya Masu (IEICE Electron. Express, 2013)

A 0.5-V 2.5-GHz high-gain low-power regenerative amplifier based on Colpitts oscillator topology in 65-nm CMOS. - Taisuke Hamada; Hao Jiang; Yiming Fang; Hiroyuki Ito; Noboru Ishihara; Kazuya Masu (APCCAS, 2014)

A 950μW 5.5-GHz low voltage PLL with digitally-calibrated ILFD and linearized varactor. - Sho Ikeda; Tatsuya Kamimura; Sang-yeop Lee; Hiroyuki Ito; Noboru Ishihara; Kazuya Masu (ASP-DAC, 2014)

A 0.52-V 5.7-GHz low noise sub-sampling PLL with dynamic threshold MOSFET. - Sho Ikeda; Sang-yeop Lee; Hiroyuki Ito; Noboru Ishihara; Kazuya Masu (A-SSCC, 2014)

An ultra-low-power RF transceiver with a 1.5-pJ/bit maximally-digital impulse-transmitter and an 89.5-μW super-regenerative RSSI. - Hiroyuki Ito; Yoshihiro Yoneda; Taiki Ibe; Taisuke Hamada; Noboru Ishihara; Kazuya Masu; Shoichi Masui; Youichi Momiyama (A-SSCC, 2014)

An ultra low power pH-monitoring IC with a duty-cycling wireless FM-transmitter. - Yusuke Shiino; Hiroyuki Ito; Taku Fujiwara; Noboru Ishihara; Hisashi Yamanouchi; Hiroki Tanabe; Satoshi Nomura; Toshifumi Konishi; Katsuyuki Machida; Kazuya Masu (ISCAS, 2014)

Hypersphere Sampling for Accelerating High-Dimension and Low-Failure Probability Circuit-Yield Analysis. - Shiho Hagiwara; Takanori Date; Kazuya Masu; Takashi Sato 001 (IEICE Trans. Electron., 2014)

A Sub-1mW Class-C-VCO-Based Low Voltage PLL with Ultra-Low-Power Digitally-Calibrated ILFD in 65nm CMOS. - Sho Ikeda; Sang-yeop Lee; Tatsuya Kamimura; Hiroyuki Ito; Noboru Ishihara; Kazuya Masu (IEICE Trans. Electron., 2014)

State-Dependence of On-Chip Power Distribution Network Capacitance. - Koh Yamanaga; Shiho Hagiwara; Ryo Takahashi; Kazuya Masu; Takashi Sato 001 (IEICE Trans. Electron., 2014)

A Variability-Aware Adaptive Test Flow for Test Quality Improvement. - Michihiro Shintani; Takumi Uezono; Tomoyuki Takahashi; Kazumi Hatayama; Takashi Aikyo; Kazuya Masu; Takashi Sato 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

A 0.5-V 5.8-GHz low-power asymmetrical QPSK/OOK transceiver for wireless sensor network. - Sho Ikeda; Sang-yeop Lee; Shin Yonezawa; Yiming Fang; Motohiro Takayasu; Taisuke Hamada; Yosuke Ishikawa; Hiroyuki Ito; Noboru Ishihara; Kazuya Masu (ASP-DAC, 2015)

A 0.5-V 1.56-mW 5.5-GHz RF transceiver IC module with J-shaped folded monopole antenna. - Yosuke Ishikawa; Sang-yeop Lee; Shin Yonezawa; Sho Ikeda; Yiming Fang; Taisuke Hamada; Hiroyuki Ito; Noboru Ishihara; Kazuya Masu (ISCAS, 2015)

13.8 A 5.8GHz RF-powered transceiver with a 113μW 32-QAM transmitter employing the IF-based quadrature backscattering technique. - Atsushi Shirane; Haowei Tan; Yiming Fang; Taiki Ibe; Hiroyuki Ito; Noboru Ishihara; Kazuya Masu (ISSCC, 2015)

RF-Powered Transceiver With an Energy- and Spectral-Efficient IF-Based Quadrature Backscattering Transmitter. - Atsushi Shirane; Yiming Fang; Haowei Tan; Taiki Ibe; Hiroyuki Ito; Noboru Ishihara; Kazuya Masu (IEEE J. Solid State Circuits, 2015)

Development of high sensitivity CMOS-MEMS inertia sensor and its application to early-stage diagnosis of Parkinson's disease. - Kazuya Masu; Daisuke Yamane; Katsuyuki Machida; Masato Sone; Yoshihiro Miyake (ESSCIRC, 2016)

Simulation and evaluation of PV power generation for energy management system using SPICE. - Yuta Oshima; Hiroshi Oguma; Noboru Ishihara; Kazuya Masu (ICTC, 2016)

A damping constant model for proof-mass structure design of MEMS inertial sensor by multi-layer metal technology. - Toshifumi Konishi; Teruaki Safu; Katsuyuki Machida; Daisuke Yamane; Masato Sone; Kazuya Masu; Hiroshi Toshiyoshi (IEEE SENSORS, 2016)

A design of spring constant arranged for MEMS accelerometer by multi-layer metal technology. - Daisuke Yamane; Toshifumi Konishi; Teruaki Safu; Hiroshi Toshiyoshi; Masato Sone; Kazuya Masu; Katsuyuki Machida (NEMS, 2016)

Environmental Data Recovery using Polynomial Regression for Large-scale Wireless Sensor Networks. - Kohei Ohba; Yoshihiro Yoneda; Koji Kurihara; Takashi Suganuma; Hiroyuki Ito; Noboru Ishihara; Kunihiko Gotoh; Koichiro Yamashita; Kazuya Masu (SENSORNETS, 2016)

An 8.865-GHz -244dB-FOM high-frequency piezoelectric resonator-based cascaded fractional-N PLL with sub-ppb-order channel adjusting technique. - Sho Ikeda; Hiroyuki Ito; Akifumi Kasamatsu; Yosuke Ishikawa; Takayoshi Obara; Naoki Noguchi; Koji Kamisuki; Yao Jiyang; Shinsuke Hara; Ruibing Dong; Shiro Dosho; Noboru Ishihara; et al. (VLSI Circuits, 2016)

Path Clustering for Test Pattern Reduction of Variation-Aware Adaptive Path Delay Testing. - Michihiro Shintani; Takumi Uezono; Kazumi Hatayama; Kazuya Masu; Takashi Sato 001 (J. Electron. Test., 2016)

Evaluation and modeling of adhesion layer in shock-protection structure for MEMS accelerometer. - Daisuke Yamane; Toshifumi Konishi; Teruaki Safu; Hiroshi Toshiyoshi; Masato Sone; Kazuya Masu; Katsuyuki Machida (Microelectron. Reliab., 2016)

Design of high-frequency piezoelectric resonator-based cascaded fractional-N PLL with sub-ppb-order channel adjusting technique. - Yosuke Ishikawa; Sho Ikeda; Hiroyuki Ito; Akifumi Kasamatsu; Takayoshi Obara; Naoki Noguchi; Koji Kamisuki; Yao Jiyang; Shinsuke Hara; Ruibing Dong; Shiro Dosho; Noboru Ishihara; et al. (ASP-DAC, 2017)

Estimation of energy self-sufficiency rate by EMS simulation using SPICE. - Yuta Oshima; Iwao Mizumoto; Hiroshi Oguma; Noboru Ishihara; Kazuya Masu (ICTC, 2017)

A study on young's modulus of electroplated gold cantilevers for MEMS devices. - Hideaki Nakajima; Tso-Fu Mark Chang; Chun-Yi Chen; Toshifumi Konishi; Katsuyuki Machida; Hiroshi Toshiyoshi; Daisuke Yamane; Kazuya Masu; Masato Sone (NEMS, 2017)

A - 244-dB FOM High-Frequency Piezoelectric Resonator-Based Cascaded Fractional-N PLL With Sub-ppb-Order Channel-Adjusting Technique. - Sho Ikeda; Hiroyuki Ito; Akifumi Kasamatsu; Yosuke Ishikawa; Takayoshi Obara; Naoki Noguchi; Koji Kamisuki; Yao Jiyang; Shinsuke Hara; Ruibing Dong; Shiro Dosho; Noboru Ishihara; et al. (IEEE J. Solid State Circuits, 2017)

A 0.18-µm CMOS time-domain capacitive-sensor interface for sub-1mG MEMS accelerometers. - Motohiro Takayasu; Shiro Dosho; Hiroyuki Ito; Daisuke Yamane; Toshifumi Konishi; Katsuyuki Machida; Noboru Ishihara; Kazuya Masu (IEICE Electron. Express, 2018)

High-Sensitivity Inertial Sensor Module to Measure Hidden Micro Muscular Sounds. - Tatsuya Koga; Katsuyuki Machida; Yoshihiro Miyake; Kazuya Masu; Takashi Ichikawa; Naoto Tanaka; Taiki Ogata; Hiroki Ora; Daisuke Yamane; Noboru Ishihara; Hiroyuki Ito; Masato Sone (BioCAS, 2019)

Fabrication of Au-Cu Alloy/Ti Layered Micro-Cantilevers and the Long-Term Structure Stability. - Kyotaro Nitta; Masato Sone; Haochun Tang; Chun-Yi Chen; Tso-Fu Mark Chang; Daisuke Yamane; Shinichi Iida; Katsuyuki Machida; Hiroyuki Ito; Kazuya Masu (IEEE SENSORS, 2019)

Current-Starved Cross-Coupled CMOS Inverter Rings as Versatile Generators of Chaotic and Neural-Like Dynamics Over Multiple Frequency Decades. - Ludovico Minati; Mattia Frasca; Natsue Yoshimura; Leonardo Ricci; Pawel Oswiecimka; Yasuharu Koike; Kazuya Masu; Hiroyuki Ito (IEEE Access, 2019)

Distributed Sensing Via Inductively Coupled Single-Transistor Chaotic Oscillators: A New Approach and Its Experimental Proof-of-Concept. - Ludovico Minati; Korkut Kaan Tokgoz; Mattia Frasca; Yasuharu Koike; Jacopo Iannacci; Natsue Yoshimura; Kazuya Masu; Hiroyuki Ito (IEEE Access, 2020)

A Simplified Analytical Damping Constant Model for Perforated Proof Mass Structure of MEMS Capacitive Accelerometer by Multi-Layer Metal Technology. - Kohei Shibata; Akihiro Uchiyama; Akira Onishi; Shinichi Iida; Toshifumi Konishi; Noboru Ishihara; Katsuyuki Machida; Kazuya Masu; Hiroyuki Ito (IEEE SENSORS, 2021)