A Generalized Execution Model for Programming on Reconfigurable Architectures and an Architecture Supporting the Model. - Kazuya Tanigawa; Tetsuo Hironaka; Akira Kojima; Noriyoshi Yoshida (FPL, 2002)

A coarse-grained reconfigurable architecture with low cost configuration data compression mechanism. - Kazuya Tanigawa; Takashi Kawasaki; Tetsuo Hironaka (FPT, 2003)

Design of superscalar processor with multi-bank register file. - Tadashi Saito 002; Moto Maeda; Tetsuo Hironaka; Kazuya Tanigawa; Tetsuya Sueyoshi; Ken-ichi Aoyama; Tetsushi Koide; Hans Jürgen Mattausch (ISCAS (4), 2005)

Unified Data/Instruction Cache with Hierarchical Multi-Port Architecture and Hidden Precharge Pipeline. - Koh Johguchi; Zhaomin Zhu; Hans Jürgen Mattausch; Tetsushi Koide; Tetsuo Hironaka; Kazuya Tanigawa (APCCAS, 2006)

Exploring compact design on high throughput coarse grained reconfigurable architectures. - Kazuya Tanigawa; Tetsuya Zuyama; Takuro Uchida; Tetsuo Hironaka (FPL, 2008)

Evaluation of compact high-throughput reconfigurable architecture based on bit-serial computation. - Kazuya Tanigawa; Tetsuo Hironaka (FPT, 2008)

Comparison of Bit Serial Computation with Bit Parallel Computation for Reconfigurable Processor. - Kazuya Tanigawa; Ken'ichi Umeda; Tetsuo Hironaka (ARC, 2010)

Design consideration for reconfigurable processor DS-HIE - Trade-off between performance and chip area. - Kazuya Tanigawa; Tetsuo Hironaka (ISOCC, 2011)

EDA Environment for Evaluating a New Switch-Block-Free Reconfigurable Architecture. - Masatoshi Nakamura; Masato Inagi; Kazuya Tanigawa; Tetsuo Hironaka; Masayuki Sato; Takashi Ishiguro (ReConFig, 2011)

A Physical Design Method for a New Memory-Based Reconfigurable Architecture without Switch Blocks. - Masatoshi Nakamura; Masato Inagi; Kazuya Tanigawa; Tetsuo Hironaka; Masayuki Sato; Takashi Ishiguro (IEICE Trans. Inf. Syst., 2012)

Development of a Trax Artificial Intelligence algorithm using path and edge. - Ryo Okuda; Tomohiro Tanaka; Keisuke Yamamoto; Takumu Yahagi; Kazuya Tanigawa (FPT, 2015)