An experimental 2-bit/cell storage DRAM for macrocell or memory-on-logic application. - Tohru Furuyama; Takashi Ohsawa; Yousei Nagahama; Hiroto Tanaka; Yohji Watanabe; Tohru Kimura; Kazuyoshi Muraoka; Kenji Natori (IEEE J. Solid State Circuits, 1989)

A latch-up-like new failure mechanism for high-density CMOS dynamic RAMs. - Tohru Furuyama; Hidemi Ishiuchi; Hiroyasu Tanaka; Yoshihisa Watanabe; Yusuke Kohyama; Tohru Kimura; Kazuyoshi Muraoka; Souichi Sugiura; Kenji Natori (IEEE J. Solid State Circuits, 1990)

A 12 MHz data cycle 4 Mb DRAM with pipeline operation. - Natsuki Kushiyama; Yohji Watanabe; Takashi Ohsawa; Kazuyoshi Muraoka; Yousei Nagahama; Tohru Furuyama (IEEE J. Solid State Circuits, 1991)

7.1 A low-power 64Gb MLC NAND-flash memory in 15nm CMOS technology. - Mario Sako; Yoshihisa Watanabe; Takao Nakajima; Jumpei Sato; Kazuyoshi Muraoka; Masaki Fujiu; Fumihiro Kouno; Michio Nakagawa; Masami Masuda; Koji Kato; Yuri Terada; Yuki Shimizu; et al. (ISSCC, 2015)

A Low Power 64 Gb MLC NAND-Flash Memory in 15 nm CMOS Technology. - Mario Sako; Yoshihisa Watanabe; Takao Nakajima; Jumpei Sato; Kazuyoshi Muraoka; Masaki Fujiu; Fumihiro Kono; Michio Nakagawa; Masami Masuda; Koji Kato; Yuri Terada; Yuki Shimizu; et al. (IEEE J. Solid State Circuits, 2016)