A 28 nm 50% power reduced 2T mask ROM with 0.72 ns read access time using column source bias. - Yukiko Umemoto; Koji Nii; Jiro Ishikawa; Kazuyoshi Okamoto; Kazutaka Mori; Kazumasa Yanagisawa (CICC, 2011)

A Test Screening Method for 28 nm HK/MG Single-Port and Dual-Port SRAMs Considering with Dynamic Stability and Read/Write Disturb Issues. - Koji Nii; Yasumasa Tsukamoto; Yuichiro Ishii; Makoto Yabuuchi; Hidehiro Fujiwara; Kazuyoshi Okamoto (Asian Test Symposium, 2012)

28 nm 50% Power-Reducing Contacted Mask Read Only Memory Macro With 0.72-ns Read Access Time Using 2T Pair Bitcell and Dynamic Column Source Bias Control Technique. - Yukiko Umemoto; Koji Nii; Jiro Ishikawa; Makoto Yabuuchi; Kazuyoshi Okamoto; Yasumasa Tsukamoto; Shinji Tanaka; Koji Tanaka; Tetsuya Matsumura; Kazutaka Mori; Kazumasa Yanagisawa (IEEE Trans. Very Large Scale Integr. Syst., 2014)