Chip-Level Performance Maximization Using ASIS (Application-Specific Interconnect Structure) Wiring Design Concept for 45 nm CMOS Generation. - Noriaki Oda; Hironori Imura; Naoyoshi Kawahara; Masayoshi Tagami; Hiroyuki Kunishima; Shuji Sone; Sadayuki Ohnishi; Kenta Yamada; Yumi Kakuhara; Makoto Sekine; Yoshihiro Hayashi; Kazuyoshi Ueno (IEICE Trans. Electron., 2007)

Present Status and Prospect of Graphene Interconnect Applications. - Kazuyoshi Ueno (IEICE Trans. Electron., 2022)