Wafer-level hybrid bonding technology with copper/polymer co-planarization. - Mayu Aoki; Kazuyuki Hozawa; Kenichi Takeda (3DIC, 2010)

Void reduction in wafer bonding by simultaneously formed ventilation channels. - Mayu Aoki; Kazuyuki Hozawa; Kenichi Takeda (3DIC, 2011)

Chip-level TSV integration for rapid prototyping of 3D system LSIs. - Kazuyuki Hozawa; Futoshi Furuta; Yuko Hanaoka; Mayu Aoki; Kenichi Takeda; Katsuyuki Sakuma; Kang Wook Lee 002; Takafumi Fukushima; Mitsumasa Koyanagi (3DIC, 2011)