Scalable unified dual-radix architecture for Montgomery multiplication in GF(P) and GF(2n). - Kazuyuki Tanimura; Ryuta Nara; Shunitsu Kohara; Kazunori Shimizu; Youhua Shi; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki (ASP-DAC, 2008)

Unified Dual-Radix Architecture for Scalable Montgomery Multiplications in GF(P) and GF(2n). - Kazuyuki Tanimura; Ryuta Nara; Shunitsu Kohara; Youhua Shi; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

ExCCel: Exploration of Complementary Cells for Efficient DPA Attack Resistivity. - Kazuyuki Tanimura; Nikil D. Dutt (HOST, 2010)

Slack-aware scheduling on Coarse Grained Reconfigurable Arrays. - Giovanni Ansaloni; Laura Pozzi 001; Kazuyuki Tanimura; Nikil D. Dutt (DATE, 2011)

LRCG: latch-based random clock-gating for preventing power analysis side-channel attacks. - Kazuyuki Tanimura; Nikil D. Dutt (CODES+ISSS, 2012)

HDRL: Homogeneous Dual-Rail Logic for DPA Attack Resistive Secure Circuit Design. - Kazuyuki Tanimura; Nikil D. Dutt (IEEE Embed. Syst. Lett., 2012)

Integrated Kernel Partitioning and Scheduling for Coarse-Grained Reconfigurable Arrays. - Giovanni Ansaloni; Kazuyuki Tanimura; Laura Pozzi 001; Nikil D. Dutt (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

Petabyte-Scale Row-Level Operations in Data Lakehouses. - Anton Okolnychyi; Chao Sun; Kazuyuki Tanimura; Russell Spitzer; Ryan Blue; Szehon Ho; Yufei Gu; Vishwanath Lakkundi; D. B. Tsai (Proc. VLDB Endow., 2024)