An approximate voting scheme for reliable computing. - Ke Chen 018; Fabrizio Lombardi; Jie Han 001 (DATE, 2015)

Matrix multiplication by an inexact systolic array. - Ke Chen 018; Fabrizio Lombardi; Jie Han 001 (NANOARCH, 2015)

On the Nonvolatile Performance of Flip-Flop/SRAM Cells With a Single MTJ. - Ke Chen 018; Jie Han 001; Fabrizio Lombardi (IEEE Trans. Very Large Scale Integr. Syst., 2015)

On the Restore Operation in MTJ-Based Nonvolatile SRAM Cells. - Ke Chen 018; Jie Han 001; Fabrizio Lombardi (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Design and analysis of an approximate 2D convolver. - Ke Chen 018; Fabrizio Lombardi; Jie Han 001 (DFT, 2016)

Partially universal modules for high performance logic circuit design. - Ke Chen 018; Fabrizio Lombardi; Jie Han 001 (MWSCAS, 2017)

Two Approximate Voting Schemes for Reliable Computing. - Ke Chen 018; Jie Han 001; Fabrizio Lombardi (IEEE Trans. Computers, 2017)

Design and Application of an Approximate 2-D Convolver with Error Compensation. - Ke Chen 018; Jie Han 001; Paolo Montuschi; Weiqiang Liu 001; Fabrizio Lombardi (ISCAS, 2018)

Efficient Implementations of Reduced Precision Redundancy (RPR) Multiply and Accumulate (MAC). - Ke Chen 018; Linbin Chen; Pedro Reviriego; Fabrizio Lombardi (IEEE Trans. Computers, 2019)

Profile-Based Output Error Compensation for Approximate Arithmetic Circuits. - Ke Chen 018; Weiqiang Liu 001; Jie Han 001; Fabrizio Lombardi (IEEE Trans. Circuits Syst., 2020)

Design of An Approximate FFT Processor Based on Approximate Complex Multipliers. - Jinhe Du; Ke Chen 018; Peipei Yin; Chenggang Yan 002; Weiqiang Liu 001 (ISVLSI, 2021)

Reduced Precision Redundancy for Reliable Processing of Data. - Shanshan Liu 001; Ke Chen 018; Pedro Reviriego; Weiqiang Liu 001; Ahmed Louri; Fabrizio Lombardi (IEEE Trans. Emerg. Top. Comput., 2021)

Approximate Arithmetic Circuits: Design and Applications. - Ke Chen 018; Weiqiang Liu 001; Fabrizio Lombardi (Approximate Computing, 2022)

An Energy-Efficient Approximate Floating-Point Multipliers for Wireless Communications. - Jipeng Ge; Chenggang Yan 002; Xuan Zhao; Ke Chen 018; Bi Wu; Weiqiang Liu 001 (APCCAS, 2022)

PAxC: A Probabilistic-oriented Approximate Computing Methodology for ANNs. - Pengfei Huang; Chenghua Wang; Ke Chen 018; Weiqiang Liu 001 (DATE, 2022)

An Energy-efficient and High-precision Approximate MAC with Distributed Arithmetic Circuits. - Ziying Cui; Ke Chen 018; Bi Wu; Chenggang Yan 002; Weiqiang Liu 001 (ACM Great Lakes Symposium on VLSI, 2022)

Data Stream Oriented Fine-grained Sparse CNN Accelerator with Efficient Unstructured Pruning Strategy. - Tianyang Yu; Bi Wu; Ke Chen 018; Chenggang Yan 002; Weiqiang Liu 001 (ACM Great Lakes Symposium on VLSI, 2022)

Energy-efficient Oriented Approximate Quantization Scheme for Fine-Grained Sparse Neural Network Acceleration. - Tianyang Yu; Bi Wu; Ke Chen 018; Chenggang Yan 002; Weiqiang Liu 001 (ICCD, 2022)

HEADiv: A High-accuracy Energy-efficient Approximate Divider with Error Compensation. - Hanghang Wang; Ke Chen 018; Bi Wu; Chenghua Wang; Weiqiang Liu 001; Fabrizio Lombardi (NANOARCH, 2022)

A survey of approximate arithmetic circuits and blocks. - Ke Chen 018; Peipei Yin; Weiqiang Liu 001; Fabrizio Lombardi (it Inf. Technol., 2022)

Editorial Special Issue on Circuits and Systems for Emerging Computing Paradigms. - Shanshan Liu 001; Bi Wu; Ke Chen 018; Weiqiang Liu 001; Máire O'Neill; Fabrizio Lombardi (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

GBC: An Energy-Efficient LSTM Accelerator With Gating Units Level Balanced Compression Strategy. - Bi Wu; Zhengkuan Wang; Ke Chen 018; Chenggang Yan 002; Weiqiang Liu 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

An Energy-efficient Approximate DCT Design for Image Processing (Invited). - Xu Wang; Ke Chen 018; Chenghua Wang; Weiqiang Liu 001 (ASICON, 2023)

Hardware-Efficient Accurate and Approximate FPGA Multipliers for Error-Tolerant Applications. - Haonan Wang; Ke Chen 018; Chenggang Yan 002; Bi Wu; Weiqiang Liu 001 (MWSCAS, 2023)

A High Accuracy and Hardware Efficient Adaptive Filter Design with Approximate Computing. - Wenzhuo Xie; Chenggang Yan 002; Hanghang Wang; Ke Chen 018; Bi Wu; Chenghua Wang; Weiqiang Liu 001 (MWSCAS, 2023)

VLCP: A High-Performance FPGA-based CNN Accelerator with Vector-level Cluster Pruning. - Shuo Ran; Bi Wu; Ke Chen 018; Weiqiang Liu 001 (NANOARCH, 2023)

MLiM: High-Performance Magnetic Logic in-Memory Scheme With Unipolar Switching SOT-MRAM. - Bi Wu; Haonan Zhu; Ke Chen 018; Chenggang Yan 002; Weiqiang Liu 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

An Energy-Efficient Computing-in-Memory (CiM) Scheme Using Field-Free Spin-Orbit Torque (SOT) Magnetic RAMs. - Bi Wu; Haonan Zhu; Dayane Reis; Zhaohao Wang; Ying Wang 001; Ke Chen 018; Weiqiang Liu 001; Fabrizio Lombardi; Xiaobo Sharon Hu (IEEE Trans. Emerg. Top. Comput., 2023)

Approximate Softmax Functions for Energy-Efficient Deep Neural Networks. - Ke Chen 018; Yue Gao; Haroon Waris; Weiqiang Liu 001; Fabrizio Lombardi (IEEE Trans. Very Large Scale Integr. Syst., 2023)

Hardware Efficient Successive-Cancellation Polar Decoders Using Approximate Computing. - Chenggang Yan 002; Yuxuan Cui; Ke Chen 018; Bi Wu; Weiqiang Liu 001 (IEEE J. Emerg. Sel. Topics Circuits Syst., 2023)

Exact and Approximate Squarers for Error-Tolerant Applications. - Ke Chen 018; Chenyu Xu; Haroon Waris; Weiqiang Liu 001; Paolo Montuschi; Fabrizio Lombardi (IEEE Trans. Computers, 2023)

A Time Efficient Comprehensive Model of Approximate Multipliers for Design Space Exploration. - Ziying Cui; Ke Chen 018; Bi Wu; Chenggang Yan 002; Yu Gong; Weiqiang Liu 001 (ARITH, 2024)

Most Significant One-Driven Shifting Dynamic Efficient Multipliers for Large Language Models. - Bin Gong; Ke Chen 018; Pengfei Huang; Bi Wu; Weiqiang Liu 001 (ISCAS, 2024)

A High-accuracy Time-efficient Error Metric Model for Approximate Computing Circuits. - Shouji Chen; Ke Chen 018; Ziying Cui; Weiqiang Liu 001 (ISVLSI, 2024)

Guest Editorial: Special Section on "Approximate Data Processing: Computing, Storage and Applications". - Ke Chen 018; Shanshan Liu 001; Weiqiang Liu 001; Fabrizio Lombardi; Nader Bagherzadeh (IEEE Trans. Emerg. Top. Comput., 2024)

Label-Efficient Point Cloud Semantic Segmentation: A Holistic Active Learning Approach. - Xian Shi; Lile Cai; Ke Chen 018; Chuan Sheng Foo; Kui Jia; Xun Xu 002 (World Sci. Annu. Rev. Artif. Intell., 2024)

Fully Learnable Hyperdimensional Computing Framework With Ultratiny Accelerator for Edge-Side Applications. - Tianyang Yu; Bi Wu; Ke Chen 018; Gong Zhang 002; Weiqiang Liu 001 (IEEE Trans. Computers, 2024)

Edge-Side Fine-Grained Sparse CNN Accelerator With Efficient Dynamic Pruning Scheme. - Bi Wu; Tianyang Yu; Ke Chen 018; Weiqiang Liu 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

Toward Efficient Retraining: A Large-Scale Approximate Neural Network Framework With Cross-Layer Optimization. - Tianyang Yu; Bi Wu; Ke Chen 018; Chenggang Yan 002; Weiqiang Liu 001 (IEEE Trans. Very Large Scale Integr. Syst., 2024)

A Potential Enabler for High-Performance In-Memory Multi-Bit Arithmetic Schemes With Unipolar Switching SOT-MRAM. - Haonan Zhu; Bi Wu; Tianyang Yu; Ke Chen 018; Chenggang Yan 002; Weiqiang Liu 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

AttnACQ: Attentioned-AutoCorrelation-Based Query for Hyperdimensional Associative Memory. - Tianyang Yu; Bi Wu; Ke Chen 018; Gong Zhang 002; Weiqiang Liu 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

High-Performance Co-Processing Architecture Using SOT-MRAM-Based In-memory Computing Scheme. - Kai Tian; Bi Wu; Ke Chen 018; Weiqiang Liu 001 (ISCAS, 2025)

LAHDC: Logic-Aggregation-Based Query for Embedded Hyperdimensional Computing Accelerator. - Tianyang Yu; Bi Wu; Ke Chen 018; Gong Zhang 002; Weiqiang Liu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

High-Radix Generalized Hyperbolic CORDIC and Its Hardware Implementation. - Hui Chen 015; Lianghua Quan; Ke Chen 018; Weiqiang Liu 001 (IEEE Trans. Computers, 2025)