A 20Gb/s full-rate linear CDR circuit with automatic frequency acquisition. - Jri Lee; Ke-Chung Wu (ISSCC, 2009)

A 20-Gb/s Full-Rate Linear Clock and Data Recovery Circuit With Automatic Frequency Acquisition. - Jri Lee; Ke-Chung Wu (IEEE J. Solid State Circuits, 2009)

A 2×25Gb/s deserializer with 2∶5 DMUX for 100Gb/s ethernet applications. - Ke-Chung Wu; Jri Lee (ISSCC, 2010)

A 2 , ˟, 25-Gb/s Receiver With 2: 5 DMUX for 100-Gb/s Ethernet. - Ke-Chung Wu; Jri Lee (IEEE J. Solid State Circuits, 2010)

A 180mW 56Gb/s DSP-Based Transceiver for High Density IOs in Data Center Switches in 7nm FinFET Technology. - Tamer A. Ali 001; Ramy Yousry; Henry Park; Ehung Chen; Po-Shuan Weng; Yi-Chieh Huang; Chun-Cheng Liu; Chien-Hua Wu; Shih-Hao Huang; Chungshi Lin; Ke-Chung Wu; Kun-Hung Tsai; et al. (ISSCC, 2019)

7.1 A 212.5Gb/s DSP-Based PAM-4 Transceiver with 50dB Loss Compensation for Large AI System Interconnects in 4nm FinFET. - Ehung Chen; Henry Park; Mohammed Abdullatif; Miguel Gandara; Ahmed ElShater; Amr Khashaba; Shih-Hao Huang; Tsz-Bin Liu; Atharav Atharav; Joonyeong Lee; Qaiser Nehal; Mohamed Megahed; et al. (ISSCC, 2025)