High-performance, Energy-efficient, Fault-tolerant Network-on-Chip Design Using Reinforcement Learnin. - Ke Wang 030; Ahmed Louri; Avinash Karanth; Razvan C. Bunescu (DATE, 2019)

IntelliNoC: a holistic design framework for energy-efficient and reliable on-chip communication for manycores. - Ke Wang 030; Ahmed Louri; Avinash Karanth; Razvan C. Bunescu (ISCA, 2019)

A Versatile and Flexible Chiplet-based System Design for Heterogeneous Manycore Architectures. - Hao Zheng 005; Ke Wang 030; Ahmed Louri (DAC, 2020)

TSA-NoC: Learning-Based Threat Detection and Mitigation for Secure Network-on-Chip Architecture. - Ke Wang 030; Hao Zheng 005; Ahmed Louri (IEEE Micro, 2020)

CURE: A High-Performance, Low-Power, and Reliable Network-on-Chip Design Using Reinforcement Learning. - Ke Wang 030; Ahmed Louri (IEEE Trans. Parallel Distributed Syst., 2020)

Adapt-NoC: A Flexible Network-on-Chip Design for Heterogeneous Manycore Architectures. - Hao Zheng 005; Ke Wang 030; Ahmed Louri (HPCA, 2021)

AGAPE: Anomaly Detection with Generative Adversarial Network for Improved Performance, Energy, and Security in Manycore Systems. - Ke Wang 030; Hao Zheng 005; Yuan Li 029; Jiajun Li; Ahmed Louri (DATE, 2022)

FSA: An Efficient Fault-tolerant Systolic Array-based DNN Accelerator Architecture. - Yingnan Zhao 001; Ke Wang 030; Ahmed Louri (ICCD, 2022)

Ascend: A Scalable and Energy-Efficient Deep Neural Network Accelerator With Photonic Interconnects. - Yuan Li 029; Ke Wang 030; Hao Zheng 005; Ahmed Louri; Avinash Karanth (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

SGCNAX: A Scalable Graph Convolutional Neural Network Accelerator With Workload Balancing. - Jiajun Li; Hao Zheng 005; Ke Wang 030; Ahmed Louri (IEEE Trans. Parallel Distributed Syst., 2022)

SecureNoC: A Learning-Enabled, High-Performance, Energy-Efficient, and Secure On-Chip Communication Framework Design. - Ke Wang 030; Hao Zheng 005; Yuan Li 029; Ahmed Louri (IEEE Trans. Sustain. Comput., 2022)

FDMAX: An Elastic Accelerator Architecture for Solving Partial Differential Equations. - Jiajun Li; Yuxuan Zhang; Hao Zheng 005; Ke Wang 030 (ISCA, 2023)

Simulation Study of Ferroresonance on Secondary Side of Main Transformer in a 500kV System. - Chuanzong Zhu; Shichang Li; Yong Li; Jiajun Li; Gang Li; Ke Wang 030; Yifeng Shi (iSPEC, 2023)

GShuttle: Optimizing Memory Access Efficiency for Graph Convolutional Neural Network Accelerators. - Jiajun Li; Ke Wang 030; Hao Zheng 005; Ahmed Louri (J. Comput. Sci. Technol., 2023)

An Efficient Hardware Accelerator Design for Dynamic Graph Convolutional Network (DGCN) Inference. - Yingnan Zhao 001; Ke Wang 030; Jiaqi Yang; Ahmed Louri (DAC, 2024)

A Flexible Hybrid Interconnection Design for High-Performance and Energy-Efficient Chiplet-Based Systems. - Md. Tareq Mahmud; Ke Wang 030 (IEEE Comput. Archit. Lett., 2024)

Algorithmic Strategies for Sustainable Reuse of Neural Network Accelerators with Permanent Faults. - Youssef A. Ait Alama; Sampada Sakpal; Ke Wang 030; Razvan C. Bunescu; Avinash Karanth; Ahmed Louri (CoRR, 2024)

Morph-GCNX: A Universal Architecture for High-Performance and Energy-Efficient Graph Convolutional Network Acceleration. - Ke Wang 030; Hao Zheng 005; Jiajun Li; Ahmed Louri (IEEE Trans. Sustain. Comput., 2024)

OPT-GCN: A Unified and Scalable Chiplet-Based Accelerator for High-Performance and Energy-Efficient GCN Computation. - Yingnan Zhao 001; Ke Wang 030; Ahmed Louri (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

A High-Performance and Flexible Accelerator for Dynamic Graph Convolutional Networks. - Yingnan Zhao 001; Ke Wang 030; Ahmed Louri (DATE, 2025)

Learning-Enabled Denial-of-Service (DoS) Attack Detection and Mitigation for Chiplet-Based Hybrid Interconnection Network. - Md. Tareq Mahmud; Ke Wang 030 (ACM Great Lakes Symposium on VLSI, 2025)