Matrix-Based Test Vector Decompression Using an Embedded Processor. - Kedarnath J. Balakrishnan; Nur A. Touba (DFT, 2002)

Scan-Based BIST Diagnosis Using an Embedded Processor. - Kedarnath J. Balakrishnan; Nur A. Touba (DFT, 2003)

Deterministic Test Vector Decompression in Software Using Linear Operations. - Kedarnath J. Balakrishnan; Nur A. Touba (VTS, 2003)

Re-configurable embedded core test protocol. - Seongmoon Wang; Srimat T. Chakradhar; Kedarnath J. Balakrishnan (ASP-DAC, 2004)

Relating entropy theory to test data compression. - Kedarnath J. Balakrishnan; Nur A. Touba (ETS, 2004)

Improving Encoding Efficiency for Linear Decompressors Using Scan Inversion. - Kedarnath J. Balakrishnan; Nur A. Touba (ITC, 2004)

Matrix-based software test data decompression for systems-on-a-chip. - Kedarnath J. Balakrishnan; Nur A. Touba (J. Syst. Archit., 2004)

Emerging Techniques for Test Data Compression. - Kedarnath J. Balakrishnan (Asian Test Symposium, 2005)

Compressing Functional Tests for Microprocessors. - Kedarnath J. Balakrishnan; Nur A. Touba; Srinivas Patil (Asian Test Symposium, 2005)

Reconfigurable Linear Decompressors Using Symbolic Gaussian Elimination. - Kedarnath J. Balakrishnan; Nur A. Touba (DATE, 2005)

XWRC: externally-loaded weighted random pattern testing for input test data compression. - Seongmoon Wang; Kedarnath J. Balakrishnan; Srimat T. Chakradhar (ITC, 2005)

Efficient unknown blocking using LFSR reseeding. - Seongmoon Wang; Kedarnath J. Balakrishnan; Srimat T. Chakradhar (DATE, 2006)

PIDISC: Pattern Independent Design Independent Seed Compression Technique. - Kedarnath J. Balakrishnan; Seongmoon Wang; Srimat T. Chakradhar (VLSI Design, 2006)

Improving Linear Test Data Compression. - Kedarnath J. Balakrishnan; Nur A. Touba (IEEE Trans. Very Large Scale Integr. Syst., 2006)

Test cost reduction for SoC using a combined approach to test data compression and test scheduling. - Quming Zhou; Kedarnath J. Balakrishnan (DATE, 2007)

Efficient Scan-Based BIST Using Multiple LFSRs and Dictionary Coding. - Kedarnath J. Balakrishnan (VLSI Design, 2007)

RTL Test Point Insertion to Reduce Delay Test Volume. - Kedarnath J. Balakrishnan; Lei Fang (VTS, 2007)

Relationship Between Entropy and Test Data Compression. - Kedarnath J. Balakrishnan; Nur A. Touba (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Test Access Mechanism for Multiple Identical Cores. - Grady Giles; Jing Wang; Anuja Sehgal; Kedarnath J. Balakrishnan; James Wingfield (ITC, 2008)

X-Block: An Efficient LFSR Reseeding-Based Method to Block Unknowns for Temporal Compactors. - Seongmoon Wang; Kedarnath J. Balakrishnan; Wenlong Wei (IEEE Trans. Computers, 2008)

Test Access Mechanism in the Quad-Core AMD Opteron Microprocessor. - Kedarnath J. Balakrishnan; Grady Giles; James Wingfield (IEEE Des. Test Comput., 2009)