Charge-transferred presensing, negatively precharged word-line, and temperature-insensitive power-up schemes for low-voltage DRAMs. - Jae-Yoon Sim; Kee-Won Kwon; Ki-Chul Chun (IEEE J. Solid State Circuits, 2004)

An 8Gb/s/pin 9.6ns Row-Cycle 288Mb Deca-Data Rate SDRAM with an I/O Error-Detection Scheme. - Kyu-Hyoun Kim; Uksong Kang; Hoeju Chung; Dukha Park; Woo-Seop Kim; Young-Chan Jang; Moon-Sook Park; Hoon Lee; Jinyoung Kim; Jung Sunwoo; Hwan-Wook Park; Hyun-Kyung Kim; et al. (ISSCC, 2006)

A low power CMOS compatible embedded EEPROM for passive RFID tag. - Kyoung-Su Lee; Jung-Hoon Chun; Kee-Won Kwon (Microelectron. J., 2010)

A Power-Efficient Voltage Upconverter for Embedded EEPROM Application. - Jong-Min Baek; Jung-Hoon Chun; Kee-Won Kwon (IEEE Trans. Circuits Syst. II Express Briefs, 2010)

A study on accelerated built-in self test of multi-Gb/s high speed interfaces. - Seong-Won Kang; Jung-Hoon Chun; Young-Hyun Jun; Kee-Won Kwon (NESEA, 2011)

A Digitally Controlled Oscillator With Wide Frequency Range and Low Supply Sensitivity. - Seong-Young Seo; Jung-Hoon Chun; Young-Hyun Jun; Seok Kim; Kee-Won Kwon (IEEE Trans. Circuits Syst. II Express Briefs, 2011)

A 3.0 Gb/s clock data recovery circuits based on digital DLL for clock-embedded display interface. - Jae-Wook Kwon; Xuefan Jin; Gyoo-Cheol Hwang; Jung-Hoon Chun; Kee-Won Kwon (ESSCIRC, 2012)

A low-power dual-PFD phase-rotating PLL with a PFD controller for 5Gb/s serial links. - Jun-Han Bae; Kyoung-Ho Kim; Seok Kim; Kee-Won Kwon; Jung-Hoon Chun (ISCAS, 2012)

A low-power two-line inversion method for driving LCD panels. - Sung-Pil Choi; Gyoo-Cheol Hwang; Young-Hyun Jun; Kee-Won Kwon; Jung-Hoon Chun (ISCAS, 2012)

0.37mW/Gb/s low power SLVS transmitter for battery powered applications. - Youngkyun Jeong; Yoon-Chul Choi; Eun-Ji Choi; Seogheon Ham; Kee-Won Kwon; Young-Hyun Jun; Jung-Hoon Chun (ISCAS, 2012)

A Dual Charge Pump for Quiescent Touch Sensor Power Supply. - Jong-Min Baek; Dong-Jin Seo; Jung-Hoon Chun; Kee-Won Kwon (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

A tracked oversampling digital data recovery for Low Latency, fast acquisition, and high jitter tolerance. - June-Hee Lee; Sang-Hoon Kim; Jongshin Shin; Dong-Chul Choi; Kee-Won Kwon; Jung-Hoon Chun (MWSCAS, 2013)

A fully digital clock and data recovery with fast frequency offset acquisition technique for MIPI LLI applications. - June-Hee Lee; Sang-Hoon Kim; Young-Hyun Jun; Kee-Won Kwon; Jung-Hoon Chun (IEICE Electron. Express, 2013)

An all-digital PLL with supply insensitive digitally controlled oscillator. - Seong-Young Seo; Jung-Hoon Chun; Young-Hyun Jun; Kee-Won Kwon (IEICE Electron. Express, 2013)

Power-Efficient Fast Write and Hidden Refresh of ReRAM Using an ADC-Based Sense Amplifier. - Sang-Yun Kim; Jong-Min Baek; Dong-Jin Seo; Jae-Koo Park; Jung-Hoon Chun; Kee-Won Kwon (IEEE Trans. Circuits Syst. II Express Briefs, 2013)

A 12.5-Gb/s near-GND transceiver for wire-line UHD video interfaces. - Seok Kim; Jung-Myung Kang; Xuefan Jin; Se-Ung Park; Ja-Hoon Jin; Kee-Won Kwon; Jung-Hoon Chun; Jung Ho Lee; Jun Young Park; Dae Young Lee (ISCAS, 2014)

A 5-Gbit/s CDR circuit with 1.4 mW multi-PFD phase rotating PLL. - Kyoung-Ho Kim; Jun-Han Bae; Young-Hyun Jun; Kee-Won Kwon (IEICE Electron. Express, 2014)

A 6.4-Gb/s Voltage-Mode Near-Ground Receiver With a One-Tap Data and Edge DFE. - Seok Kim; Eun-Young Jin; Kee-Won Kwon; Jintae Kim; Jung-Hoon Chun (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

A 5.2-Gb/s Low-Swing Voltage-Mode Transmitter With an AC-/DC-Coupled Equalizer and a Voltage Offset Generator. - Seok Kim; Youngkyun Jeong; Mira Lee; Kee-Won Kwon; Jung-Hoon Chun (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

CMOS Charge Pump With No Reversion Loss and Enhanced Drivability. - Joung-Yeal Kim; Su-Jin Park; Kee-Won Kwon; Bai-Sun Kong; Joo-Sun Choi; Young-Hyun Jun (IEEE Trans. Very Large Scale Integr. Syst., 2014)

A digital DLL with 4-cycle lock time and 1/4 NAND-delay accuracy. - Sung-Yong Kim; Xuefan Jin; Jung-Hoon Chun; Kee-Won Kwon (A-SSCC, 2015)

Full chip integration of 3-d cross-point ReRAM with leakage-compensating write driver and disturbance-aware sense amplifier. - Sangheon Lee; Jeonghwan Song; Changhyuk Seong; Jiyong Woo; Jong-Moon Choi; Soon-Chan Kwon; Ho-Joon Kim; Hyun-Suk Kang; Soo Gil Kim; Hoe Gwon Jung; Kee-Won Kwon; Hyunsang Hwang (VLSI Circuits, 2016)

Local NOR and global NAND match-line architecture for high performance CAM. - Sung-Gi Ahn; Kee-Won Kwon (MWSCAS, 2017)

A Fast and Reliable Cross-Point Three-State/Cell ReRAM. - Soon-Chan Kwon; Jong-Min Baek; Jong-Moon Choi; Kee-Won Kwon (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Low Power Search Engine using Non-volatile Memory based TCAM with Priority Encoding and Selective Activation of Search Line and Match Line. - Cheol Kim; Rak-Joo Sung; Sung-Gi Ahn; Jisu Min; Kee-Won Kwon (ISCAS, 2018)

A 4-GHz Sub-harmonically Injection-Locked Phase-Locked Loop with Self-Calibrated Injection Timing and Pulsewidth. - Xuefan Jin; Dong-Seok Kang; Youngjun Ko; Kee-Won Kwon; Jung-Hoon Chun (A-SSCC, 2019)

Low Power 3T-2R Non-Volatile TCAM Cell with Dual Match-line. - Dojong Cheon; Kee-Won Kwon (ICEIC, 2019)

High performance 4T-2R Non-Volatile TCAM with NMOS Booster. - Byoungkon Jo; Kee-Won Kwon (ICEIC, 2019)

A 16x16 Programmable Anlaog Vector Matrix Multiplier using CMOS compatible Floating gate device. - Yong-Hyun Kim; Jong-Moon Choi; Je-Joong Woo; Eun-Je Park; Sang-Won Kim; Kee-Won Kwon (ICEIC, 2019)

CMOS-Compatible Learning Device for Neuromorphic Synapse Application using Adjustable Hot Carrier Injections. - Je-Joong Woo; Jong-Moon Choi; Kee-Won Kwon (MWSCAS, 2019)

Power Efficient and Reliable Nonvolatile TCAM With Hi-PFO and Semi-Complementary Driver. - Cheol Kim; Sung-Gi Ahn; Jisu Min; Kee-Won Kwon (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

A Study of Read Margin Enhancement for 3T2R Nonvolatile TCAM Using Adaptive Bias Training. - Jisu Min; Cheol Kim; Sung-Yong Kim; Kee-Won Kwon (IEEE Trans. Very Large Scale Integr. Syst., 2019)

A 35x10 Charge-Trap Synaptic Memory for 57xMatrix Recognition. - Eun-Je Park; Jong-Moon Choi; Do-Wan Kwon; Je-Joong Woo; Kee-Won Kwon (AICAS, 2020)

Architecture-Accuracy Co-optimization of ReRAM-based Low-cost Neural Network Processor. - Segi Lee; Sugil Lee; Jongeun Lee; Jong-Moon Choi; Do-Wan Kwon; Seung-Kwang Hong; Kee-Won Kwon (ACM Great Lakes Symposium on VLSI, 2020)

A High Efficiency Variable Stage and Frequency Charge Pump for Wide Range ISPP. - Sang-Won Kim; Jae-Hyuk Yang; Eun-Je Park; Jong-Moon Choi; Kee-Won Kwon (ISCAS, 2020)

Smart Adaptive Refresh for Optimum Refresh Interval Tracking using in-DRAM ECC. - Do-Yeon Kim; Kee-Won Kwon (MWSCAS, 2020)

A 4-GHz Sub-Harmonically Injection-Locked Phase-Locked Loop With Self-Calibrated Injection Timing and Pulsewidth. - Xuefan Jin; Woosung Park; Dong-Seok Kang; Youngjun Ko; Kee-Won Kwon; Jung-Hoon Chun (IEEE J. Solid State Circuits, 2020)

A Non-linear Input Converter Inversely Pre-distorted Against Nonlinear Behavior of FG-based Neuromorphic Synaptic Devices. - Jin-Young Hwang; Kee-Won Kwon (ISOCC, 2021)

Binary/Ternary Vector Matrix Multiplier with 3T-2R CBRAM Cell. - Hwan-Jin Joo; Kee-Won Kwon (ISOCC, 2021)

High Linearity Vector Matrix Multiplier using Bootstrapping and Pre-Emphasis Charging of Non-linear Charge-Trap Synaptic Devices. - Se-Won Yun; Young-Taek Ryu; Kee-Won Kwon (MWSCAS, 2021)

Implementation of an On-Chip Learning Neural Network IC Using Highly Linear Charge Trap Device. - Jong-Moon Choi; Do-Wan Kwon; Je-Joong Woo; Eun-Je Park; Kee-Won Kwon (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

Dynamic Power Reduction of TCAM Using Selective Precharging of Match Lines. - Su-Yeon Doo; Kee-Won Kwon (IEEE Big Data, 2022)

A 6.23-bit FG-based Neuromorphic Synaptic Device with Extended Input Range by Linearity Improvement. - Young-Taek Ryu; Kee-Won Kwon (ICEIC, 2022)

Fast and Efficient Offset Compensation by Noise-Aware Pre-Charge and Operation of DRAM Bit Line Sense Amplifier. - Tae-Bin Kim; Hyun-Jin Kim; Kee-Won Kwon (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

Highly Linear Charging/Discharging of Charge Trap FET Using Regulated Single Pulse for Neural Accelerator. - Jeong-In Choi; Seo-Yoon Lee; Chan-Woong Park; Jin-Gon Oh; Ji Hoon Kang 003; Kee-Won Kwon (ICEIC, 2024)

Si Bridge With Chessboard Patterned Interconnect (CPI): Enabling High Density, High Efficiency Heterogeneous Integration. - Seungkyu Kim; Kihun Ok; Kee-Won Kwon (ICEIC, 2024)

A Highly-Sensitive and Compact Interconnect Delay Monitoring Circuit for 3-Dimensional System Packages. - Seung-Mo Noh; Seungkyu Kim; Seo-Yoon Lee; Kee-Won Kwon (ICEIC, 2024)

An Invariant Interconnect Delay Monitoring Circuit for 3D System Scaling. - Seung-Mo Noh; Kee-Won Kwon (ISOCC, 2024)

Optimization of TSV-Induced Stress Using a Slanted Profile in a Backside TSV Process. - Seki Hong; Jimyoung Lee; Jongwook Jeon; Kee-Won Kwon (ICEIC, 2025)

A Comparative Analysis of Middle-of-Line Contact Architectures for Complementary FETs. - Seungkyu Kim; Johyeon Kim; Gunhee Choi; Kee-Won Kwon; Jongwook Jeon (IEEE Access, 2025)