An Efficient Path Delay Fault Coverage Estimator. - Keerthi Heragu; Michael L. Bushnell; Vishwani D. Agrawal (DAC, 1994)

FACTS: fault coverage estimation by test vector sampling. - Keerthi Heragu; Vishwani D. Agrawal; Michael L. Bushnell (VTS, 1994)

Statistical methods for delay fault coverage analysis. - Keerthi Heragu; Vishwani D. Agrawal; Michael L. Bushnell (VLSI Design, 1995)

Fault coverage estimation by test vector sampling. - Keerthi Heragu; Vishwani D. Agrawal; Michael L. Bushnell (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995)

SIGMA: a simulator for segment delay faults. - Keerthi Heragu; Janak H. Patel; Vishwani D. Agrawal (ICCAD, 1996)

Improving accuracy in path delay fault coverage estimation. - Keerthi Heragu; Janak H. Patel; Vishwani D. Agrawal (VLSI Design, 1996)

Segment delay faults: a new fault model. - Keerthi Heragu; Janak H. Patel; Vishwani D. Agrawal (VTS, 1996)

Fast identification of untestable delay faults using implications. - Keerthi Heragu; Janak H. Patel; Vishwani D. Agrawal (ICCAD, 1997)

Improving a nonenumerative method to estimate path delay fault coverage. - Keerthi Heragu; Vishwani D. Agrawal; Michael L. Bushnell; Janak H. Patel (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997)

Where We Might Stumble with Embedded-System Test. - Keerthi Heragu (VTS, 1998)

New Techniques to Verify Timing Correctness of Integrated Circuits - Keerthi Heragu (1998)

A Test Generator for Segment Delay Faults. - Keerthi Heragu; Janak H. Patel; Vishwani D. Agrawal (VLSI Design, 1999)

Testing of Dynamic Logic Circuits Based on Charge Sharing. - Keerthi Heragu; Manish Sharma; Rahul Kundu; R. D. (Shawn) Blanton (VTS, 2001)

Test vector generation for charge sharing failures in dynamic logic. - Keerthi Heragu; Manish Sharma; Rahul Kundu; Ronald D. Blanton (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002)

A 6.25-Gb/s binary transceiver in 0.13-μm CMOS for serial data transmission across high loss legacy backplane channels. - Robert Payne; Paul E. Landman; Bhavesh Bhakta; Sridhar Ramaswamy; Song Wu; John D. Powers; M. Ulvi Erdogan; Ah-Lyan Yee; Richard Gu; Lin Wu; Yiqun Xie; Bharadwaj Parthasarathy; et al. (IEEE J. Solid State Circuits, 2005)

A 45nm 3.5G Baseband-and-Multimedia Application Processor using Adaptive Body-Bias and Ultra-Low-Power Techniques. - Gordon Gammie; Alice Wang; Minh Chau; Sumanth Gururajarao; Robert Pitts; Fabien Jumel; Stacey Engel; Philippe Royannez; Rolf Lagerquist; Hugh Mair; Jeff Vaccani; Greg Baldwin; et al. (ISSCC, 2008)