A Die Selection and Matching Method with Two Stages for Yield Enhancement of 3-D Memories. - Wooheon Kang; Changwook Lee; Keewon Cho; Sungho Kang 001 (Asian Test Symposium, 2013)

A Delay Test Architecture for TSV With Resistive Open Defects in 3-D Stacked Memories. - Hyungsu Sung; Keewon Cho; Kunsang Yoon; Sungho Kang 001 (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Near optimal repair rate built-in redundancy analysis with very small hardware overhead. - Woosung Lee; Keewon Cho; Jooyoung Kim; Sungho Kang 001 (ISQED, 2015)

Discussion of cost-effective redundancy architectures. - Keewon Cho; Jooyoung Kim; Hayoung Lee; Sungho Kang 001 (ISOCC, 2016)

A Survey of Repair Analysis Algorithms for Memories. - Keewon Cho; Wooheon Kang; Hyungjun Cho; Changwook Lee; Sungho Kang 001 (ACM Comput. Surv., 2016)

An efficient built-in self-repair scheme for area reduction. - Keewon Cho; Young-Woo Lee; Sungyoul Seo; Sungho Kang 001 (ISOCC, 2017)

Hardware-Efficient Built-In Redundancy Analysis for Memory With Various Spares. - Jooyoung Kim; Woosung Lee; Keewon Cho; Sungho Kang 001 (IEEE Trans. Very Large Scale Integr. Syst., 2017)

2-D Failure Bitmap Compression Using Line Fault Marking Method. - Keewon Cho; Young-Woo Lee; Sungyoul Seo; Sungho Kang 001 (ISOCC, 2018)

A Statistic-Based Scan Chain Reordering for Energy-Quality Scalable Scan Test. - Sungyoul Seo; Keewon Cho; Young-Woo Lee; Sungho Kang 001 (IEEE J. Emerg. Sel. Topics Circuits Syst., 2018)

Fault Group Pattern Matching With Efficient Early Termination for High-Speed Redundancy Analysis. - Hayoung Lee; Kiwon Cho; Donghyun Kim; Sungho Kang 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Fast Built-In Redundancy Analysis Based on Sequential Spare Line Allocation. - Hayoung Lee; Jooyoung Kim; Keewon Cho; Sungho Kang 001 (IEEE Trans. Reliab., 2018)

An Efficient BIRA Utilizing Characteristics of Spare Pivot Faults. - Keewon Cho; Young-Woo Lee; Sungyoul Seo; Sungho Kang 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

Fail Memory Configuration Set for RA Estimation. - Hayoung Lee; Keewon Cho; Sungho Kang 001; Wooheon Kang; Seungtaek Lee; Woosik Jeong (ITC, 2020)

A 1ynm 1.25V 8Gb, 16Gb/s/pin GDDR6-based Accelerator-in-Memory supporting 1TFLOPS MAC Operation and Various Activation Functions for Deep-Learning Applications. - Seong Ju Lee; Kyu-Young Kim; Sanghoon Oh; Joonhong Park; Gimoon Hong; Dong Yoon Ka; Kyu-Dong Hwang; Jeongje Park; Kyeong Pil Kang; Jungyeon Kim; Junyeol Jeon; Nahsung Kim; et al. (ISSCC, 2022)