A process and environment tolerant 3V, 2 GHz VCO with 0.8 μm CMOS technology. - Keewook Jung; Changsik Yoo; Hyun-Kyu Yu; Wonchui Song; Wonchan Kim (IEEE Trans. Consumer Electron., 1999)

A 2.5-V 2.0-Gbyte/s 288-Mb packet-based DRAM with enhanced cell efficiency and noise immunity. - Kyehyun Kyung; Hi-Choon Lee; Ki-Whan Song; Ho-Sung Song; Keewook Jung; Joon-Seo Moon; Byoung-Sul Kim; Sung-Burn Cho; Changhyun Kim; Soo-In Cho (IEEE J. Solid State Circuits, 2001)

A PVT-Tolerant Low-1/f Noise Dual-Loop Hybrid PLL in 0.18µm. - Hyung-Rok Lee; Ook Kim; Keewook Jung; John Shin; Deog-Kyoon Jeong (ISSCC, 2006)