A 24 dB gain 51-68 GHz CMOS low noise amplifier using asymmetric-layout transistors. - Ning Li 009; Keigo Bunsen; Naoki Takayama; Qinghong Bu; Toshihide Suzuki; Masaru Sato 001; Tatsuya Hirose; Kenichi Okada 001; Akira Matsuzawa (ESSCIRC, 2010)

A De-Embedding Method Using Different-Length Transmission Lines for mm-Wave CMOS Device Modeling. - Naoki Takayama; Kota Matsushita; Shogo Ito; Ning Li 009; Keigo Bunsen; Kenichi Okada 001; Akira Matsuzawa (IEICE Trans. Electron., 2010)

A 60GHz 16Gb/s 16QAM low-power direct-conversion transceiver using capacitive cross-coupling neutralization in 65 nm CMOS. - Hiroki Asada; Keigo Bunsen; Kota Matsushita; Rui Murakami; Qinghong Bu; Ahmed Musa; Takahiro Sato; Tatsuya Yamaguchi; Ryo Minami; Toshihiko Ito; Kenichi Okada 001; Akira Matsuzawa (A-SSCC, 2011)

A 60GHz 16QAM/8PSK/QPSK/BPSK direct-conversion transceiver for IEEE 802.15.3c. - Kenichi Okada 001; Kota Matsushita; Keigo Bunsen; Rui Murakami; Ahmed Musa; Takahiro Sato; Hiroki Asada; Naoki Takayama; Ning Li 009; Shogo Ito; Win Chaivipas; Ryo Minami; et al. (ISSCC, 2011)

A 60-GHz 16QAM/8PSK/QPSK/BPSK Direct-Conversion Transceiver for IEEE802.15.3c. - Kenichi Okada 001; Ning Li 009; Kota Matsushita; Keigo Bunsen; Rui Murakami; Ahmed Musa; Takahiro Sato; Hiroki Asada; Naoki Takayama; Shogo Ito; Win Chaivipas; Ryo Minami; et al. (IEEE J. Solid State Circuits, 2011)

A full 4-channel 6.3Gb/s 60GHz direct-conversion transceiver with low-power analog and digital baseband circuitry. - Kenichi Okada 001; Keitarou Kondou; Masaya Miyahara; Masashi Shinagawa; Hiroki Asada; Ryo Minami; Tatsuya Yamaguchi; Ahmed Musa; Yuuki Tsukui; Yasuo Asakura; Shinya Tamonoki; Hiroyuki Yamagishi; et al. (ISSCC, 2012)

A 24 dB Gain 51-68 GHz Common Source Low Noise Amplifier Using Asymmetric-Layout Transistors. - Ning Li 009; Keigo Bunsen; Naoki Takayama; Qinghong Bu; Toshihide Suzuki; Masaru Sato 001; Yoichi Kawano; Tatsuya Hirose; Kenichi Okada 001; Akira Matsuzawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012)

Full Four-Channel 6.3-Gb/s 60-GHz CMOS Transceiver With Low-Power Analog and Digital Baseband Circuitry. - Kenichi Okada 001; Keitarou Kondou; Masaya Miyahara; Masashi Shinagawa; Hiroki Asada; Ryo Minami; Tatsuya Yamaguchi; Ahmed Musa; Yuuki Tsukui; Yasuo Asakura; Shinya Tamonoki; Hiroyuki Yamagishi; et al. (IEEE J. Solid State Circuits, 2013)

A Self-Calibrated 16GHz Subsampling-PLL-Based 30s Fast Chirp FMCW Modulator with 1.5GHz Bandwidth and 100kHz rms Error. - Qixian Shi; Keigo Bunsen; Nereo Markulic; Jan Craninckx (ISSCC, 2019)

A Self-Calibrated 16-GHz Subsampling-PLL-Based Fast-Chirp FMCW Modulator With 1.5-GHz Bandwidth. - Qixian Shi; Keigo Bunsen; Nereo Markulic; Jan Craninckx (IEEE J. Solid State Circuits, 2019)

A Redundancy-Based Background Calibration for Comparator Offset/Threshold and DAC Gain in a Ping-Pong SAR ADC. - Keigo Bunsen; Ewout Martens; Davide Dermit; Jan Craninckx (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

An Injection-Locked Ring-Oscillator-Based Fractional-N Digital PLL Supporting BLE Frequency Modulation. - Yuming He; Johan H. C. van den Heuvel; Paul Mateman; Erwin Allebes; Stefano Traferro; Johan Dijkhuis; Keigo Bunsen; Peter Vis; Arjan Breeschoten; Yao-Hong Liu; Tomohiro Matsumoto; Christian Bachmann (IEEE J. Solid State Circuits, 2022)