A bipolar-PMOS merged basic cell for 0.8 mu m BiCMOS sea of gates. - Toshiaki Hanibuchi; Masahiro Ueda; Keiichi Higashitani; Masahiro Hatanaka; Koichiro Mashiko; Akiharu Tada (IEEE J. Solid State Circuits, 1991)

A 622-Mb/s 8*8 ATM switch chip set with shared multibuffer architecture. - Harufusa Kondoh; Hiromi Notani; Hideaki Yamanaka; Keiichi Higashitani; Hirotaka Saito; Isamu Hayashi; Shigeki Kohama; Yoshio Matsuda; Kazuyoshi Oshima; Masao Nakaya (IEEE J. Solid State Circuits, 1993)