A 0.65-ns, 72-kb ECL-CMOS RAM macro for a 1-Mb SRAM. - Hiroalu Nambu; Kazuo Kanetani; Youji Idei; Tom Masuda; Keiichi Higeta; Masayuki Ohayashi; Masami Usami; Kunihiko Yamaguchi; Toshiyuki Kikuchi; Takahide Ikeda; Kenichi Ohhata; Takeshi Kusunoki; et al. (IEEE J. Solid State Circuits, 1995)

A soft-error-immune 0.9-ns 1.15-Mb ECL-CMOS SRAM with 30-ps 120 k logic gates and on-chip test circuitry. - Keiichi Higeta; Masami Usami; Masayuki Ohayashi; Yasuhiro Fujimura; Masahiko Nishiyama; Satoru Isomura; Kunihiko Yamaguchi; Youji Idei; Hiroaki Nambu; Kenichi Ohhata; Nadateru Hanta (IEEE J. Solid State Circuits, 1996)

A 1.8-ns access, 550-MHz, 4.5-Mb CMOS SRAM. - Hiroaki Nambu; Kazuo Kanetani; Kaname Yamasaki; Keiichi Higeta; Masami Usami; Yasuhiro Fujimura; Kazumasa Ando; Takeshi Kusunoki; Kunihiko Yamaguchi; Noriyuki Homma (IEEE J. Solid State Circuits, 1998)

Built-in self-test for GHz embedded SRAMs using flexible pattern generator and new repair algorithm. - Shigeru Nakahara; Keiichi Higeta; Masaki Kohno; Toshiaki Kawamura; Keizo Kakitani (ITC, 1999)

A 550-ps access 900-MHz 1-Mb ECL-CMOS SRAM. - Hiroaki Nambu; Kazuo Kanetani; Kaname Yamasaki; Keiichi Higeta; Masami Usami; Masahiko Nishiyama; Kenichi Ohhata; Fumihiko Arakawa; Takeshi Kusunoki; Kunihiko Yamaguchi; Atsuo Hotta; Noriyuki Homma (IEEE J. Solid State Circuits, 2000)

Power reduction techniques for a 1-Mb ECL-CMOS SRAM with an access time of 550 ps and an operating frequency of 900 MHz. - Kenichi Ohhata; Fumihiko Arakawa; Takeshi Kusunoki; Hiroaki Nambu; Kazuo Kanetani; Kaname Yamasaki; Keiichi Higeta; Masami Usami; Masahiko Nishiyama; Kunihiko Yamaguchi; Noriyuki Homma; Atsuo Hotta (IEEE J. Solid State Circuits, 2000)

Synonym hit RAM - a 500-MHz CMOS SRAM macro with 576-bit parallel comparison and parity check functions. - Takeshi Suzuki; Keiichi Higeta; Yasuhiro Fujimura; Kazumasa Ando; Hiroaki Nambu; Ryo Yamagata; Atsuo Hotta; Kunihiko Yamaguchi (IEEE J. Solid State Circuits, 2000)

External memory BIST for system-in-package. - Kaname Yamasaki; Iwao Suzuki; Azumi Kobayashi; Keiichi Horie; Yasuharu Kobayashi; Hideyuki Aoki; Hideki Hayashi; Kenichi Tada; Koki Tsutsumida; Keiichi Higeta (ITC, 2005)

3.2 multi-standard 185fsrms 0.3-to-28Gb/s 40dB backplane signal conditioner with adaptive pattern-match 36-Tap DFE and data-rate-adjustment PLL in 28nm CMOS. - Takashi Kawamoto; Takayasu Norimatsu; Kenji Kogo; Fumio Yuki; Norio Nakajima; Masatoshi Tsuge; Tatsunori Usugi; Tomofumi Hokari; Hideki Koba; Takemasa Komori; Junya Nasu; Tsuneo Kawamata; et al. (ISSCC, 2015)

3.3 A 25Gb/s multistandard serial link transceiver for 50dB-loss copper cable in 28nm CMOS. - Takayasu Norimatsu; Takashi Kawamoto; Kenji Kogo; Naohiro Kohmu; Fumio Yuki; Norio Nakajima; Takashi Muto; Junya Nasu; Takemasa Komori; Hideki Koba; Tatsunori Usugi; Tomofumi Hokari; et al. (ISSCC, 2016)