An Algorithm to Eliminate All Complex Triangles in a Maximal Planar Graph for Use in VLSI floorplan. - Shuji Tsukiyama; Keiichi Koike; Isao Shirakawa (Algorithmic Aspects of VLSI Layout, 1993)

A 1-GHz/0.9-mW CMOS/SIMOX divide-by-128/129 dual-modulus prescaler using a divide-by-2/3 synchronous counter. - Yuichi Kado; Masao Suzuki; Keiichi Koike; Yasuhisa Omura; Katsutoshi Izumi (IEEE J. Solid State Circuits, 1993)

High-speed, low-power, bipolar standard cell design methodology for Gbit/s signal processing. - Keiichi Koike; Kenji Kawai; Akira Onozawa; Yuichiro Takei; Yoshiji Kobayashi; Haruhiko Ichino (IEEE J. Solid State Circuits, 1998)

A 557-mW, 2.5-Gbit/s SONET/SDH regenerator-section terminating LSI chip using low-power bipolar-LSI design. - Kenji Kawai; Keiichi Koike; Yuichiro Takei; Akira Onozawa; Hitoshi Obara; Haruhiko Ichino (IEEE J. Solid State Circuits, 1999)

A 2Gb/s network processor with a 24mW IPsec offload for residential gateways. - Yukikuni Nishida; Kenji Kawai; Keiichi Koike (ISSCC, 2010)