40 nm Dual-port and two-port SRAMs for automotive MCU applications under the wide temperature range of -40 to 170°C with test screening against write disturb issues. - Yoshisato Yokoyama; Yuichiro Ishii; Koji Tanaka; Tatsuya Fukuda; Yoshiki Tsujihashi; Atsushi Miyanishi; Shinobu Asayama; Keiichi Maekawa; Kazutoshi Shiba; Koji Nii (A-SSCC, 2014)

A Perpetuum Mobile 32bit CPU with 13.4pJ/cycle, 0.14µA sleep current using Reverse Body Bias Assisted 65nm SOTB CMOS technology. - Koichiro Ishibashi; Nobuyuki Sugii; Kimiyoshi Usami; Hideharu Amano; Kazutoshi Kobayashi; Cong-Kha Pham; Hideki Makiyama; Yoshiki Yamamoto; Hirofumi Shinohara; Toshiaki Iwamatsu; Yasuo Yamaguchi; Hidekazu Oda; et al. (COOL Chips, 2014)

0.39-V, 18.26-µW/MHz SOTB CMOS Microcontroller with embedded atom switch ROM. - Toshitsugu Sakamoto; Yukihide Tsuji; Munehiro Tada; Hideki Makiyama; Takumi Hasegawa; Yoshiki Yamamoto; Shinobu Okanishi; Keiichi Maekawa; Naoki Banno; Makoto Miyamura; Koichiro Okamoto; Noriyuki Iguchi; et al. (COOL Chips, 2015)

A Silicon-on-Thin-Buried-Oxide CMOS Microcontroller with Embedded Atom-Switch ROM. - Toshitsugu Sakamoto; Yukihide Tsuji; Munehiro Tada; Hideki Makiyama; Takumi Hasegawa; Yoshiki Yamamoto; Shinobu Okanishi; Keiichi Maekawa; Naoki Banno; Makoto Miyamura; Koichiro Okamoto; Noriyuki Iguchi; et al. (IEEE Micro, 2015)

A 65nm Silicon-on-Thin-Box (SOTB) Embedded 2T-MONOS Flash Achieving 0.22 pJ/bit Read Energy with 64 MHz Access for IoT Applications. - Ken Matsubara; Tsutomu Nagasawa; Yoshinobu Kaneda; Hidenori Mitani; Hiroshi Sato; Takashi Iwase; Yasunobu Aoki; Keiichi Maekawa; Hideaki Yamakoshi; Takashi Ito; Hiroyuki Kondo; Takashi Kono (VLSI Circuits, 2019)