On-line Optimization of Avoidance Ability for Redundant Manipulator. - Keiji Ikeda; Hiroshi Tanaka; Tong-xiao Zhang; Mamoru Minami; Yasushi Mae (IROS, 2006)

New layout design methodology for monolithically integrated 3D CMOS logic circuits based on parasitics engineering. - Chika Tanaka; Keiji Ikeda; Masumi Saitoh (ESSDERC, 2015)

Charge-based Neuromorphic Cell by InGaZnO Transistor and Implementation of Simple Scheme Spike-Timing-Dependent Plasticity. - Chika Tanaka; Keiji Ikeda (ISCAS, 2018)