CD-ROM System Based on the NEWS Workstation. - Keiji Kimura; Akihide Demura; Tatsuya Igarashi; Yukio Takeyari (COMPCON, 1988)

Detection of small cracks in the chain of a trolley conveyor with an infrared camera. - Hajime Yamashina; Susumu Okumura; Keiji Kimura (J. Intell. Manuf., 1993)

Multigrain Automatic Parallelization in Japanese Millennium Project IT21 Advanced Parallelizing Compiler. - Hironori Kasahara; Motoki Obata; Kazuhisa Ishizaka; Keiji Kimura; Hiroki Kaminaga; Hirofumi Nakano; Kouhei Nagasawa; Akiko Murai; Hiroki Itagaki; Jun Shirako (PARELEC, 2002)

Static Coarse Grain Task Scheduling with Cache Optimization Using OpenMP. - Hirofumi Nakano; Kazuhisa Ishizaka; Motoki Obata; Keiji Kimura; Hironori Kasahara (Int. J. Parallel Program., 2003)

Performance of OSCAR Multigrain Parallelizing Compiler on SMP Servers. - Kazuhisa Ishizaka; Takamichi Miyamoto; Jun Shirako; Motoki Obata; Keiji Kimura; Hironori Kasahara (LCPC, 2004)

Multigrain parallel processing on compiler cooperative chip multiprocessor. - Keiji Kimura; Yasutaka Wada; Hirofumi Nakano; Takeshi Kodaka; Jun Shirako; Kazuhisa Ishizaka; Hironori Kasahara (Interaction between Compilers and Computer Architectures, 2005)

Performance Evaluation of Compiler Controlled Power Saving Scheme. - Jun Shirako; Munehiro Yoshida; Naoto Oshiyama; Yasutaka Wada; Hirofumi Nakano; Hiroaki Shikano; Keiji Kimura; Hironori Kasahara (ISHPC, 2005)

Compiler Control Power Saving Scheme for Multi Core Processors. - Jun Shirako; Naoto Oshiyama; Yasutaka Wada; Hiroaki Shikano; Keiji Kimura; Hironori Kasahara (LCPC, 2005)

A 4320MIPS Four-Processor Core SMP/AMP with Individually Managed Clock Frequency for Low Power Consumption. - Yutaka Yoshida; Tatsuya Kamei; Kiyoshi Hayase; Shinichi Shibahara; Osamu Nishii; Toshihiro Hattori; Atsushi Hasegawa; Masashi Takada; Naohiko Irie; Kunio Uchiyama; Toshihiko Odaka; Kiwamu Takada; et al. (ISSCC, 2007)

Software-cooperative power-efficient heterogeneous multi-core for media processing. - Hiroaki Shikano; Masaki Ito; Kunio Uchiyama; Toshihiko Odaka; Akihiro Hayashi; Takeshi Masuura; Masayoshi Mase; Jun Shirako; Yasutaka Wada; Keiji Kimura; Hironori Kasahara (ASP-DAC, 2008)

Parallelization with Automatic Parallelizing Compiler Generating Consumer Electronics Multicore API. - Takamichi Miyamoto; Saori Asaka; Hiroki Mikami; Masayoshi Mase; Yasutaka Wada; Hirofumi Nakano; Keiji Kimura; Hironori Kasahara (ISPA, 2008)

An 8640 MIPS SoC with Independent Power-Off Control of 8 CPUs and 8 RAMs by An Automatic Parallelizing Compiler. - Masayuki Ito; Toshihiro Hattori; Yutaka Yoshida; Kiyoshi Hayase; Tomoichi Hayashi; Osamu Nishii; Yoshihiko Yasu; Atsushi Hasegawa; Masashi Takada; Hiroyuki Mizuno; Kunio Uchiyama; Toshihiko Odaka; et al. (ISSCC, 2008)

Power-Aware Compiler Controllable Chip Multiprocessor. - Hiroaki Shikano; Jun Shirako; Yasutaka Wada; Keiji Kimura; Hironori Kasahara (IEICE Trans. Electron., 2008)

Heterogeneous Multi-Core Architecture That Enables 54x AAC-LC Stereo Encoding. - Hiroaki Shikano; Masaki Ito; Masafumi Onouchi; Takashi Todaka; Takanobu Tsunoda; Tomoyuki Kodama; Kunio Uchiyama; Toshihiko Odaka; Tatsuya Kamei; Ei Nagahama; Manabu Kusaoke; Yusuke Nitta; et al. (IEEE J. Solid State Circuits, 2008)

Green Multicore-SoC Software-Execution Framework with Timely-Power-Gating Scheme. - Masafumi Onouchi; Keisuke Toyama 003; Tohru Nojiri; Makoto Sato; Masayoshi Mase; Jun Shirako; Mikiko Sato; Masashi Takada; Masayuki Ito; Hiroyuki Mizuno; Mitaro Namiki; Keiji Kimura; et al. (ICPP, 2009)

OSCAR API for Real-Time Low-Power Multicores and Its Performance on Multicores and SMP Servers. - Keiji Kimura; Masayoshi Mase; Hiroki Mikami; Takamichi Miyamoto; Jun Shirako; Hironori Kasahara (LCPC, 2009)

A 45nm 37.3GOPS/W heterogeneous multi-core SoC. - Yoichi Yuyama; Masayuki Ito; Yoshikazu Kiyoshige; Yusuke Nitta; Shigezumi Matsui; Osamu Nishii; Atsushi Hasegawa; Makoto Ishikawa; Tetsuya Yamada; Junichi Miyakoshi; Koichi Terada; Tohru Nojiri; et al. (ISSCC, 2010)

Parallelizing Compiler Framework and API for Power Reduction and Software Productivity of Real-Time Heterogeneous Multicores. - Akihiro Hayashi; Yasutaka Wada; Takeshi Watanabe; Takeshi Sekiguchi; Masayoshi Mase; Jun Shirako; Keiji Kimura; Hironori Kasahara (LCPC, 2010)

Geyser-2: The second prototype CPU with fine-grained run-time power gating. - Lei Zhao; Daisuke Ikebuchi; Yoshiki Saito; M. Kamata; Naomi Seki; Yu Kojima; Hideharu Amano; Satoshi Koyama; Tatsunori Hashida; Y. Umahashi; D. Masuda; Kimiyoshi Usami; et al. (ASP-DAC, 2011)

Evaluation of Power Consumption at Execution of Multiple Automatically Parallelized and Power Controlled Media Applications on the RP2 Low-Power Multicore. - Hiroki Mikami; Shumpei Kitaki; Masayoshi Mase; Akihiro Hayashi; Mamoru Shimaoka; Keiji Kimura; Masato Edahiro; Hironori Kasahara (LCPC, 2011)

A 45-nm 37.3 GOPS/W Heterogeneous Multi-Core SOC with 16/32 Bit Instruction-Set General-Purpose Core. - Osamu Nishii; Yoichi Yuyama; Masayuki Ito; Yoshikazu Kiyoshige; Yusuke Nitta; Makoto Ishikawa; Tetsuya Yamada; Junichi Miyakoshi; Yasutaka Wada; Keiji Kimura; Hironori Kasahara; Hideo Maejima (IEICE Trans. Electron., 2011)

A Parallelizing Compiler Cooperative Heterogeneous Multicore Processor Architecture. - Yasutaka Wada; Akihiro Hayashi; Takeshi Masuura; Jun Shirako; Hirofumi Nakano; Hiroaki Shikano; Keiji Kimura; Hironori Kasahara (Trans. High Perform. Embed. Archit. Compil., 2011)

Enhancing the Performance of a Multiplayer Game by Using a Parallelizing Compiler. - Yasir I. M. Al-Dosary; Keiji Kimura; Hironori Kasahara; Seinosuke Narita (Int. J. Intell. Games Simul., 2012)

Automatic parallelization, performance predictability and power control for mobile-applications. - Dominic Hillenbrand; Akihiro Hayashi; Hideo Yamamoto; Keiji Kimura; Hironori Kasahara (COOL Chips, 2013)

Parallelization of automotive engine control software on embedded multi-core processor using OSCAR compiler. - Yohei Kanehagi; Dan Umeda; Akihiro Hayashi; Keiji Kimura; Hironori Kasahara (COOL Chips, 2013)

OSCAR Compiler Controlled Multicore Power Reduction on Android Platform. - Hideo Yamamoto; Tomohiro Hirano; Kohei Muto; Hiroki Mikami; Takashi Goto 003; Dominic Hillenbrand; Moriyuki Takamura; Keiji Kimura; Hironori Kasahara (LCPC, 2013)

Reconciling application power control and operating systems for optimal power and performance. - Dominic Hillenbrand; Yuuki Furuyama; Akihiro Hayashi; Hiroki Mikami; Keiji Kimura; Hironori Kasahara (ReCoSoC, 2013)

Evaluation of Automatic Power Reduction with OSCAR Compiler on Intel Haswell and ARM Cortex-A9 Multicores. - Tomohiro Hirano; Hideo Yamamoto; Shuhei Iizuka; Kohei Muto; Takashi Goto 003; Tamami Wake; Hiroki Mikami; Moriyuki Takamura; Keiji Kimura; Hironori Kasahara (LCPC, 2014)

Coarse Grain Task Parallelization of Earthquake Simulator GMS Using OSCAR Compiler on Various Cc-NUMA Servers. - Mamoru Shimaoka; Yasutaka Wada; Keiji Kimura; Hironori Kasahara (LCPC, 2015)

Multigrain Parallelization for Model-Based Design Applications Using the OSCAR Compiler. - Dan Umeda; Takahiro Suzuki; Hiroki Mikami; Keiji Kimura; Hironori Kasahara (LCPC, 2015)

Annotatable systrace: an extended Linux ftrace for tracing a parallelized program. - Daichi Fukui; Mamoru Shimaoka; Hiroki Mikami; Dominic Hillenbrand; Hideo Yamamoto; Keiji Kimura; Hironori Kasahara (SEPS@SPLASH, 2015)

An Android Systrace Extension for Tracing Wakelocks. - Bui Duc Binh; Keiji Kimura (CSE/EUC/DCABES, 2016)

Mixed Integer Nonlinear Program for Minimization of Akaike's Information Criterion. - Keiji Kimura; Hayato Waki (ICMS, 2016)

Automatic Local Memory Management for Multicores Having Global Address Space. - Kouhei Yamamoto; Tomoya Shirakawa; Yoshitake Oki; Akimasa Yoshida; Keiji Kimura; Hironori Kasahara (LCPC, 2016)

Accelerating Multicore Architecture Simulation Using Application Profile. - Keiji Kimura; Gakuho Taguchi; Hironori Kasahara (MCSoC, 2016)

2-Step Power Scheduling with Adaptive Control Interval for Network Intrusion Detection Systems on Multicores. - Lau Phi Tuong; Keiji Kimura (MCSoC, 2016)

Architecture Design for the Environmental Monitoring System over the Winter Season. - Koichiro Yamashita; Takahisa Suzuki; Hongchun Li; Chen Ao; Yi Xu 020; Jun Tian; Keiji Kimura; Hironori Kasahara (MobiWac, 2016)

Reducing parallelizing compilation time by removing redundant analysis. - Jixin Han; Rina Fujino; Ryota Tamura; Mamoru Shimaoka; Hiroki Mikami; Moriyuki Takamura; Sachio Kamiya; Kazuhiko Suzuki; Takahiro Miyajima; Keiji Kimura; Hironori Kasahara (SEPS@SPLASH, 2016)

If-Conversion Optimization using Neuro Evolution of Augmenting Topologies. - Reem Elkhouly; Keiji Kimura; Ahmed El-Mahdy 002 (CoRR, 2016)

Android Video Processing System Combined with Automatically Parallelized and Power Optimized Code by OSCAR Compiler. - Bui Duc Binh; Tomohiro Hirano; Hiroki Mikami; Hideo Yamamoto; Keiji Kimura; Hironori Kasahara (J. Inf. Process., 2016)

A Mixed Integer Quadratic Formulation for the Shortest Vector Problem. - Keiji Kimura; Hayato Waki (CREST Crypto-Math Project, 2017)

Multicore Cache Coherence Control by a Parallelizing Compiler. - Hironori Kasahara; Keiji Kimura; Boma A. Adhi; Yuhei Hosokawa; Yohei Kishimoto; Masayoshi Mase (COMPSAC (1), 2017)

Software Cache Coherent Control by Parallelizing Compiler. - Boma A. Adhi; Masayoshi Mase; Yuhei Hosokawa; Yohei Kishimoto; Taisuke Onishi; Hiroki Mikami; Keiji Kimura; Hironori Kasahara (LCPC, 2017)

Application of mixed integer quadratic program to shortest vector problems. - Keiji Kimura; Hayato Waki; Masaya Yasuda (JSIAM Lett., 2017)

Message from the CAP Organizing Committee. - Cristina Seceleanu; Keiji Kimura (COMPSAC (1), 2018)

Minimization of Akaike's information criterion in linear regression analysis via mixed integer nonlinear program. - Keiji Kimura; Hayato Waki (Optim. Methods Softw., 2018)

Fast and Highly Optimizing Separate Compilation for Automatic Parallelization. - Tohma Kawasumi; Ryota Tamura; Yuya Asada; Jixin Han; Hiroki Mikami; Keiji Kimura; Hironori Kasahara (HPCS, 2019)

Performance of Static and Dynamic Task Scheduling for Real-Time Engine Control System on Embedded Multicore Processor. - Yoshitake Oki; Hiroki Mikami; Hikaru Nishida; Dan Umeda; Keiji Kimura; Hironori Kasahara (LCPC, 2019)

Performance Evaluation on NVMM Emulator Employing Fine-Grain Delay Injection. - Yu Omori; Keiji Kimura (NVMSA, 2019)

Cascaded DMA Controller for Speedup of Indirect Memory Access in Irregular Applications. - Tomoya Kashimata; Toshiaki Kitamura; Keiji Kimura; Hironori Kasahara (IA3@SC, 2019)

Efficient Checkpointing with Recompute Scheme for Non-volatile Main Memory. - Mohammad A. Alshboul; Hussein Elnawawy; Reem Elkhouly; Keiji Kimura; James Tuck 001; Yan Solihin (ACM Trans. Archit. Code Optim., 2019)

Scalable and Fast Lazy Persistency on GPUs. - Ardhi Wiratama Baskara Yudha; Keiji Kimura; Huiyang Zhou; Yan Solihin (IISWC, 2020)

Compiler Software Coherent Control for Embedded High Performance Multicore. - Boma A. Adhi; Tomoya Kashimata; Ken Takahashi; Keiji Kimura; Hironori Kasahara (IEICE Trans. Electron., 2020)

Local Memory Mapping of Multicore Processors on an Automatic Parallelizing Compiler. - Yoshitake Oki; Yuto Abe; Kazuki Yamamoto; Kohei Yamamoto; Tomoya Shirakawa; Akimasa Yoshida; Keiji Kimura; Hironori Kasahara (IEICE Trans. Electron., 2020)

Compiler-support for Critical Data Persistence in NVM. - Reem Elkhouly; Mohammad A. Alshboul; Akihiro Hayashi; Yan Solihin; Keiji Kimura (ACM Trans. Archit. Code Optim., 2020)

Parallelizing Compiler Translation Validation Using Happens-Before and Task-Set. - Jixin Han; Tomofumi Yuki; Michelle Mills Strout; Dan Umeda; Hironori Kasahara; Keiji Kimura (CANDAR (Workshops), 2021)

Performance Evaluation of OSCAR Multi-target Automatic Parallelizing Compiler on Intel, AMD, Arm and RISC-V Multicores. - Birk Martin Magnussen; Tohma Kawasumi; Hiroki Mikami; Keiji Kimura; Hironori Kasahara (LCPC, 2021)

OSCAR Parallelizing and Power Reducing Compiler and API for Heterogeneous Multicores : (Invited Paper). - Hironori Kasahara; Keiji Kimura; Toshiaki Kitamura; Hiroki Mikami; Kazutaka Morita; Kazuki Fujita; Kazuki Yamamoto; Tohma Kawasumi (PEHC@SC, 2021)

Secure Image Inference Using Pairwise Activation Functions. - Jonas T. Agyepong; Mostafa Soliman; Yasutaka Wada; Keiji Kimura; Ahmed El-Mahdy 002 (IEEE Access, 2021)

Non-Volatile Main Memory Emulator for Embedded Systems Employing Three NVMM Behaviour Models. - Yu Omori; Keiji Kimura (IEICE Trans. Inf. Syst., 2021)

Durable Queue Implementations Built on a Formally Defined Strand Persistency Model. - Jixin Han; Keiji Kimura (J. Inf. Process., 2021)

Parallelizing Factory Automation Ladder Programs by OSCAR Automatic Parallelizing Compiler. - Tohma Kawasumi; Yuta Tsumura; Hiroki Mikami; Tomoya Yoshikawa; Takero Hosomi; Shingo Oidate; Keiji Kimura; Hironori Kasahara (LCPC, 2022)

Lightweight Array Contraction by Trace-Based Polyhedral Analysis. - Hugo Thievenaz; Keiji Kimura; Christophe Alias (ISC Workshops, 2022)

Accelerating Data Dependence Profiling Through Abstract Interpretation of Loop Instructions. - Mostafa M. Abbas; Mostafa I. Soliman; Sherif I. Rabia; Keiji Kimura; Ahmed El-Mahdy 002 (IEEE Access, 2022)

Open-Source Hardware Memory Protection Engine Integrated With NVMM Simulator. - Yu Omori; Keiji Kimura (IEEE Comput. Archit. Lett., 2022)

Data stream clustering for low-cost machines. - Christophe Cérin; Keiji Kimura; Mamadou Sow (J. Parallel Distributed Comput., 2022)

Cross-Domain Few-Shot Sparse-Quantization Aware Learning for Lymphoblast Detection in Blood Smear Images. - Dina Aboutahoun; Rami Zewail; Keiji Kimura; Mostafa I. Soliman (ACPR (3), 2023)

Parallel Verification in RISC-V Secure Boot. - Akihiro Saiki; Yu Omori; Keiji Kimura (MCSoC, 2023)

Lightweight Histological Tumor Classification Using a Joint Sparsity-Quantization Aware Training Framework. - Dina Aboutahoun; Rami Zewail; Keiji Kimura; Mostafa I. Soliman (IEEE Access, 2023)

Ideal Parametrisation Estimation for Variational Quantum Circuit Classifiers Using Machine Learning. - Mostafa Fathi; Walid Gomaa 001; Yasutaka Wada; Keiji Kimura; Kazunori Ueda; Ahmed El-Mahdy 002 (QCE, 2024)

Engineering systems analysis of mobility in Odawara city: New transportation services impacts on community engagement. - Keiji Kimura; Bryan R. Moser (Syst. Eng., 2024)

Enclave Application Cache for RISC-V Keystone. - Takumu Umezawa; Akihiro Saiki; Keiji Kimura (EuroS&P (Workshops), 2025)