A high-speed, low-power bipolar digital circuit for Gb/s LSI's: current mirror control logic. - Keiji Kishine; Yoshiji Kobayashi; Haruhiko Ichino (IEEE J. Solid State Circuits, 1997)

A 2.5-Gb/s clock and data recovery IC with tunable jitter characteristics for use in LANs and WANs. - Keiji Kishine; Noboru Ishihara; Ken-ichi Takiguchi; Haruhiko Ichino (IEEE J. Solid State Circuits, 1999)

A jitter suppression technique for a 2.48832 Gb/s clock and data recovery circuit. - Kiyoshi Ishii; Keiji Kishine; Haruhiko Ichino (ISCAS, 2000)

Loop-parameter optimization of a PLL for a low-jitter 2.5-Gb/s one-chip optical receiver IC with 1: 8 DEMUX. - Keiji Kishine; Kiyoshi Ishii; Haruhiko Ichino (IEEE J. Solid State Circuits, 2002)

PLL design technique by a loop-trajectory analysis taking decision-circuit phase margin into account for over-10-Gb/s clock and data recovery circuits. - Keiji Kishine; Kyoko Fujimoto; Satomi Kusanagi; Haruhiko Ichino (IEEE J. Solid State Circuits, 2004)

Physical Layer OAM&P Signaling Method for 10 Gbit/s Ethernet Transport over Optical Networks. - Kazuhiko Terada; Kenji Kawai; Osamu Ishida; Keiji Kishine; Noboru Iwasaki; Haruhiko Ichino (IEICE Trans. Commun., 2005)

MAC protocol based on cross-layer design methodology for fast link in wireless communication systems. - Shoko Ohteru; Keiji Kishine; Haruhiko Ichino (IEICE Electron. Express, 2007)

A 16Gbps laser-diode driver with interwoven peaking inductors in 0.18-µm CMOS. - Takeshi Kuboki; Yusuke Ohtomo; Akira Tsuchiya; Keiji Kishine; Hidetoshi Onodera (CICC, 2010)

Throughput Estimation Method in Burst ACK Scheme for Optimizing Frame Size and Burst Frame Number Appropriate to SNR-Related Error Rate. - Shoko Ohteru; Keiji Kishine (IEICE Trans. Commun., 2010)

A 10.3Gbps translmpedance amplifier with mutually coupled inductors in 0.18-μm CMOS. - Shigekazu Miyawaki; Makoto Nakamura; Akira Tsuchiya; Keiji Kishine; Hidetoshi Onodera (ISOCC, 2011)

Bandwidth enhancement for high speed amplifier utilizing mutually coupled on-chip inductors. - Akira Tsuchiya; Takeshi Kuboki; Yusuke Ohtomo; Keiji Kishine; Shigekazu Miyawaki; Makoto Nakamura; Hidetoshi Onodera (ISOCC, 2011)

A 16Gb/s area-efficient LD driver with interwoven inductor in a 0.18µm CMOS. - Takeshi Kuboki; Yusuke Ohtomo; Akira Tsuchiya; Keiji Kishine; Hidetoshi Onodera (ASP-DAC, 2012)

Design method for an over-IO-Gb/s CMOS CML buffer circuit for delay control. - Keiji Kishine; Hiromi Inaba; Yusuke Ohtomo; Makoto Nakamura; Mitsuo Nakamura (MWSCAS, 2012)

Area-Effective Inductive Peaking with Interwoven Inductor for High-Speed Laser-Diode Driver for Optical Communication System. - Takeshi Kuboki; Yusuke Ohtomo; Akira Tsuchiya; Keiji Kishine; Hidetoshi Onodera (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012)

A 25-Gb/s LD driver with area-effective inductor in a 0.18-µm CMOS. - Takeshi Kuboki; Yusuke Ohtomo; Akira Tsuchiya; Keiji Kishine; Hidetoshi Onodera (ASP-DAC, 2013)

Analysis and design based on small-signal equivalent circuit for a lO-GHz ring VCO with 65-nm CMOS. - Keiji Kishine; Hiromi Inaba; Yusuke Ohtomo; Makoto Nakamura; Hiroshi Koizumi; Mitsuo Nakamura (MWSCAS, 2013)

A 65-nm CMOS burst-mode CDR based on a GVCO with symmetric loops. - Keiji Kishine; Hiroshi Inoue; Hiromi Inaba; Makoto Nakamura; Akira Tsuchiya; Hidetoshi Onodera; Hiroaki Katsurai (ISCAS, 2014)

A Multi-Rate Burst-Mode CDR Using a GVCO With Symmetric Loops for Instantaneous Phase Locking in 65-nm CMOS. - Keiji Kishine; Hiromi Inaba; Hiroshi Inoue; Makoto Nakamura; Akira Tsuchiya; Hiroaki Katsurai; Hidetoshi Onodera (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

Design of high-linearity delay detection circuit for 10-Gb/s communication system in 65-nm CMOS. - Kosuke Furuichi; Hiromu Uemura; Natsuyuki Koda; Hiromi Inaba; Keiji Kishine (ISOCC, 2016)

36-Gb/s CDR IC using simple passive loop filter combined with passive load in phase detector. - Keiji Kishine; Hiroshi Inoue; Kosuke Furuichi; Natsuyuki Koda; Hiromu Uemura; Hiromi Inaba; Makoto Nakamura; Akira Tsuchiya (ISOCC, 2016)

Proposal for sensitive frequency demodulator for 10-Gb/s transmission labeling signal system. - Natsuyuki Koda; Kosuke Furuichi; Hiromu Uemura; Hiromi Inaba; Keiji Kishine (ISOCC, 2016)

25-Gb/s clock and data recovery IC using latch-load combined with CML buffer circuit for delay generation with 65-nm CMOS. - Tomonori Tanaka; Kosuke Furuichi; Hiromu Uemura; Ryosuke Noguchi; Natsuyuki Koda; Koki Arauchi; Daichi Omoto; Hiromi Inaba; Keiji Kishine; Shinsuke Nakano; Masafumi Nogawa; Hideyuki Nosaka (ISCAS, 2017)

Compact implementation IIR filter in FPGA for noise reduction of sensor signal. - Koki Arauchi; Shohei Maki; Toshiyuki Inoue; Akira Tsuchiya; Keiji Kishine (ISOCC, 2017)

Design method for inductorless low-noise amplifiers with active shunt-feedback in 65-nm CMOS. - Toshiyuki Inoue; Akira Tsuchiya; Keiji Kishine; Makoto Nakamura (ISOCC, 2017)

FPGA-based transceiver circuit for labeling signal transmission system. - Kohei Nomura; Natsuyuki Koda; Toshiyuki Inoue; Akira Tsuchiya; Keiji Kishine (ISOCC, 2017)

A 25-Gb/s Low-Power Clock and Data Recovery with an Active-Stabilizing CML-CMOS Conversion. - Ryosuke Noguchi; Atsuto Imajo; Toshiyuki Inoue; Akira Tsuchiya; Keiji Kishine (ICECS, 2018)

A Wideband Differential VCO Based on Multiple-path Loop Architecture. - Tomotaka Tanaka; Fumiya Naito; Makoto Nakamura; Daisuke Ito; Keiji Kishine (ISOCC, 2018)

Low-Power and High-Linearity Inductorless Low-Noise Amplifiers with Active-Shunt-Feedback in 65-nm CMOS Technology. - Toshiyuki Inoue; Ryosuke Noguchi; Akira Tsuchiya; Keiji Kishine; Hidetoshi Onodera (MWSCAS, 2018)

A 25-Gb/s 13 mW clock and data recovery using C2MOS D-flip-flop in 65-nm CMOS. - Ryosuke Noguchi; Kosuke Furuichi; Hiromu Uemura; Toshiyuki Inoue; Akira Tsuchiya; Keiji Kishine; Hiroaki Katsurai; Shinsuke Nakano; Hideyuki Nosaka (VLSI-DAT, 2018)

Suitable-Compensation Circuit Design for a PAM4 Transmitter in 180-nm CMOS. - Yudai Ichii; Ryosuke Noguchi; Toshiyuki Inoue; Akira Tsuchiya; Keiji Kishine (ISOCC, 2019)

A wideband differential VCO based on double-short-path loop architecture. - Daisuke Ito; Tomotaka Tanaka; Makoto Nakamura; Keiji Kishine (ISOCC, 2019)

Frequency Discriminator Using a Simple AD Converter for Interface Systems. - Sanshiro Kimura; Atsuto Imajo; Toshiyuki Inoue; Akira Tsuchiya; Keiji Kishine (ISOCC, 2019)

Optimization Technique of Memory Traffic for FPGA-Based Image Processing System. - Kenta Nishiguchi; Toshiyuki Inoue; Akira Tsuchiya; Kazunori Ogohara; Keiji Kishine (ISOCC, 2019)

Design of Crosstalk Noise Filter for Multi-Channel Transimpedance Amplifier. - Shinya Tanimura; Akira Tsuchiya; Ryosuke Noguchi; Toshiyuki Inoue; Keiji Kishine (SoCC, 2019)

Burst-Mode CMOS Transimpedance Amplifier Based on a Regulated-Cascode Circuit with Gain-Mode Switching. - Takuya Kojima; Mamoru Kunieda; Makoto Nakamura; Daisuke Ito; Keiji Kishine (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019)

Impact of On-Chip Inductor and Power-Delivery-Network Stacking on Signal and Power Integrity. - Akira Tsuchiya; Akitaka Hiratsuka; Toshiyuki Inoue; Keiji Kishine; Hidetoshi Onodera (IEICE Trans. Electron., 2019)

Processing Time Reduction for JPEG Compression Using Pixel Array Conversion. - Rei Yamazaki; Toshiyuki Inoue; Akira Tsuchiya; Keiji Kishine (ISOCC, 2020)

Supply Noise Reduction Filter for Parallel Integrated Transimpedance Amplifiers. - Shinya Tanimura; Akira Tsuchiya; Toshiyuki Inoue; Keiji Kishine (ASP-DAC, 2021)

5-Gb/s PAM4 Transmitter IC Using Compensation Circuit in an 180-nm CMOS. - Yudai Ichii; Toshiyuki Inoue; Akira Tsuchiya; Keiji Kishine (ICEIC, 2021)

Implementation of Low-Energy LSTM with Parallel and Pipelined Algorithm in Small-Scale FPGA. - Ukyo Yoshimura; Toshiyuki Inoue; Akira Tsuchiya; Keiji Kishine (ICEIC, 2021)

A Burst-Mode TIA with Adaptive Response and Stable Operation for in-Vehicle Optical Networks. - Toshiyuki Inoue; Akira Tsuchiya; Keiji Kishine; Daisuke Ito; Yasuhiro Takahashi; Makoto Nakamura (ICECS, 2021)

Supply-Variation-Tolerant Transimpedance Amplifier Using Non-Inverting Amplifier in 180-nm CMOS. - Tomofumi Tsuchida; Akira Tsuchiya; Toshiyuki Inoue; Keiji Kishine (ASP-DAC, 2022)

Method of Estimating Positions for Multiple People in Non-Contact Vital Signs Monitoring Systems. - Masaya Kashiwagi; Toshiyuki Inoue; Masanao Okamoto; Akira Tsuchiya; Keiji Kishine (ICEIC, 2022)

A preamplifier circuit with offset-voltage control technique for 50-Gb/s CMOS PAM4 receiver. - Masaya Miyabe; Toshiyuki Inoue; Masataka Inoue; Shinya Nakashioya; Akira Tsuchiya; Keiji Kishine (ICEIC, 2022)

Capacitor Under Pad for Small Area Integration of High-Speed Signal-to-Differential Amplifier. - Akira Tsuchiya; Toshiyuki Inoue; Keiji Kishine; Yasuhiro Takahashi; Daisuke Ito; Makoto Nakamura (ICEIC, 2022)

Process Acceleration for HEVC Using Parallel Characteristics Calculation and Pixel Array Conversion. - Rei Yamazaki; Toshiyuki Inoue; Yuuki Teramura; Akira Tsuchiya; Keiji Kishine (ICEIC, 2022)

A Fine-Tuning Phase Shifter with Vector Synthesizer Using 65-nm CMOS for Beamforming in 24-GHz Band. - Masataka Inoue; Shinya Nakashioya; Toshiyuki Inoue; Akira Tsuchiya; Keiji Kishine (ICECS 2022, 2022)

A Burst-Mode TIA with Automatic Power Saving and DC Wander Reduction in 65-nm CMOS. - Toshiyuki Inoue; Akira Tsuchiya; Keiji Kishine; Daisuke Ito; Yasuhiro Takahashi; Makoto Nakamura (ICECS 2022, 2022)

A Method for Implementing LSTM-Based Multiple-People Identification System for Non-Contact Health Monitoring on Small-Scale FPGA. - Masanao Okamoto; Toshiyuki Inoue; Akira Tsuchiya; Keiji Kishine (ISOCC, 2022)

Memory-Access Optimization for Acceleration and Power Saving of FPGA-Based Image Processing. - Shungo Shimohane; Toshiyuki Inoue; Akira Tsuchiya; Keiji Kishine (ISOCC, 2022)

Smart Computational Resource Distribution System with Automatic Classification Interface for CPS. - Yuuki Teramura; Toshiyuki Inoue; Akira Tsuchiya; Keiji Kishine (ISOCC, 2022)

A 28-Gb/s VCSEL Driver with Variable Output Impedance in 65-nm CMOS. - Toshiyuki Inoue; Akira Tsuchiya; Keiji Kishine; Daisuke Ito; Yasuhiro Takahashi; Makoto Nakamura (MWSCAS, 2022)

A Small-Area Integration of Optical Receiver Using Multi-Layer Inductors and Capacitor-Under-Pad. - Akira Tsuchiya; Toshiyuki Inoue; Keiji Kishine; Yasuhiro Takahashi; Daisuke Ito; Makoto Nakamura (MWSCAS, 2022)

High-Speed, Low-Power, and Small-Area Optical Receiver in 65-nm CMOS. - Akira Tsuchiya; Toshiyuki Inoue; Keiji Kishine; Daisuke Ito; Yasuhiro Takahashi; Makoto Nakamura (ASICON, 2023)

A 4×32-Gb/s VCSEL Driver with Adaptive Feedforward Equalization in 65-nm CMOS. - Toshiyuki Inoue; Akira Tsuchiya; Keiji Kishine; Daisuke Ito; Yasuhiro Takahashi; Makoto Nakamura (ICECS, 2023)

4-ch 25-Gb/s Small and Low-power VCSEL Driver Circuit with Unbalanced CML in 65-nm CMOS. - Daisuke Ito; Yasuhiro Takahashi; Makoto Nakamura; Toshiyuki Inoue; Akira Tsuchiya; Keiji Kishine (ISOCC, 2023)

10Gb/s burst-mode driver circuit with on-chip bias switch for in-Vehicle optical networks. - Daisuke Ito; Yasuhiro Takahashi; Makoto Nakamura; Toshiyuki Inoue; Akira Tsuchiya; Keiji Kishine (IEICE Electron. Express, 2023)

Low-power and small-area 4-ch 25-Gb/s transimpedance amplifiers in 65-nm CMOS process. - Yasuhiro Takahashi; Daisuke Ito; Makoto Nakamura; Akira Tsuchiya; Toshiyuki Inoue; Keiji Kishine (IEICE Electron. Express, 2023)

A 25-Gb/s Active Feedback Transimpedance Amplifier in 65-nm CMOS. - Yasuhiro Takahashi; Daisuke Ito; Makoto Nakamura; Akira Tsuchiya; Toshiyuki Inoue; Keiji Kishine (ICEIC, 2024)

A Small-Area and Low-EPB Inductive-Peaking VCSEL Driver for a 65-nm CMOS Chip. - Toshiyuki Inoue; Akira Tsuchiya; Keiji Kishine; Daisuke Ito; Yasuhiro Takahashi; Makoto Nakamura (SOCC, 2024)

A burst-mode receiver with quick response and high consecutive identical digit tolerance for advanced intra-vehicle optical networks. - Toshiyuki Inoue; Akira Tsuchiya; Keiji Kishine; Daisuke Ito; Yasuhiro Takahashi; Makoto Nakamura (Microelectron. J., 2024)

A 16-Channel Optical Receiver Circuit for a Multicore Fiber-Based Co-Packaged Optics Module in a 65-nm CMOS Chip. - Toshiyuki Inoue; Akira Tsuchiya; Keiji Kishine; Yasuhiro Takahashi; Daisuke Ito; Makoto Nakamura (IEEE Trans. Circuits Syst. II Express Briefs, 2024)