Development of a high-performance universal computing element - PULCE. - Hajime lizuka; Yutaka Hayashi; Keikichi Tamaru; Hisashi Hara (AFIPS National Computer Conference, 1978)

System design of a special-purpose computer for LSI design rule checking. - Keikichi Tamaru; Hidetoshi Onodera (Syst. Comput. Jpn., 1987)

A cyclic A/D converter that does not require ratio-matched components. - Hidetoshi Onodera; Tetsuo Tateishi; Keikichi Tamaru (IEEE J. Solid State Circuits, 1988)

Extraction of Functional Information from Combinatorial Circuits. - M. Ohmura; Hiroto Yasuura; Keikichi Tamaru (ICCAD, 1990)

Operational-amplifier compilation with performance optimization. - Hidetoshi Onodera; Hiroyuki Kanbara; Keikichi Tamaru (IEEE J. Solid State Circuits, 1990)

Branch-and-Bound Placement for Building Block Layout. - Hidetoshi Onodera; Yo Taniguchi; Keikichi Tamaru (DAC, 1991)

Design of data-path module generators from algorithmic representations. - Vasily G. Moshnyaga; Keikichi Tamaru; Hiroto Yasuura (Synthesis for Control Dominated Circuits, 1992)

High speed merged multiplication. - Farhad Fuad Islam; Keikichi Tamaru (ICASSP (1), 1993)

Layout-driven module selection for register-transfer synthesis of sub-micron ASIC's. - Vasily G. Moshnyaga; Hiroshi Mori; Hidetoshi Onodera; Keikichi Tamaru (ICCAD, 1993)

An Architecture for Intermediate Area-time Complexity Multiplier. - Farhad Fuad Islam; Keikichi Tamaru (ISCAS, 1993)

Processing nested loop structure with data-flow dependence on a CAM-based processor HAPP. - Kuei-Ming Lu; Keikichi Tamaru (ISPAN, 1994)

A model-adaptable MOSFET parameter extraction system. - Masaki Kondo; Hidetoshi Onodera; Keikichi Tamaru (ASP-DAC, 1995)

A scheduling algorithm for synthesis of bus-partitioned architectures. - Vasily G. Moshnyaga; Fumiaki Ohbayashi; Keikichi Tamaru (ASP-DAC, 1995)

An iterative gate sizing approach with accurate delay evaluation. - Guangqiu Chen; Hidetoshi Onodera; Keikichi Tamaru (ICCAD, 1995)

A New Algorithm for Sorting Problem with Reformed CAM. - Kuei-Ming Lu; Keikichi Tamaru (ISCAS, 1995)

A Comparative Study of Switching Activity Reduction Techniques for Design of Low-Power Multipliers. - Vasily G. Moshnyaga; Keikichi Tamaru (ISCAS, 1995)

Register-Transfer Module Selection for Sub-Micron ASIC Design. - Vasily G. Moshnyaga; Yutaka Mori; Keikichi Tamaru (IEICE Trans. Inf. Syst., 1995)

High speed merged array multiplication. - Farhad Fuad Islam; Keikichi Tamaru (J. VLSI Signal Process., 1995)

Timing and Power Optimization by Gate Sizing Considering False Paths. - Guangqiu Chen; Hidetoshi Onodera; Keikichi Tamaru (Great Lakes Symposium on VLSI, 1996)

A functional memory type parallel processor for vector quantization. - Kazutoshi Kobayashi; Masayoshi Kinoshita; Masahiro Takeuchi; Hidetoshi Onodera; Keikichi Tamaru (ASP-DAC, 1997)

A current mode cyclic A/D converter with a 0.8 μm CMOS process. - Masaki Kondo; Hidetoshi Onodera; Keikichi Tamaru (ASP-DAC, 1997)

A memory efficient array architecture for full-search block matching algorithm. - Vasily G. Moshnyaga; Keikichi Tamaru (ICASSP, 1997)

A Memory Efficient Array Architecture for Real-Time Motion Estimation. - Vasily G. Moshnyaga; Keikichi Tamaru (IPPS, 1997)

A new architecture for in-memory image convolution. - Vasily G. Moshnyaga; Kazuhiro Suzuki; Keikichi Tamaru (ICASSP, 1998)

Real time low bit-rate video coding algorithm using multi-stage hierarchical vector quantization. - Kazuhiko Terada; Masahiro Takeuchi; Kazutoshi Kobayashi; Keikichi Tamaru (ICASSP, 1998)

Proposal of a timing model for CMOS logic gates driving a CRC load. - Akio Hirata; Hidetoshi Onodera; Keikichi Tamaru (ICCAD, 1998)

A power optimization method considering glitch reduction by gate sizing. - Masanori Hashimoto; Hidetoshi Onodera; Keikichi Tamaru (ISLPED, 1998)

A memory efficient array architecture for real-time motion estimation. - Vasily G. Moshnyaga; Naoto Watanabe; Keikichi Tamaru (Syst. Comput. Jpn., 1998)

Model-adaptable MOSFET parameter-extraction method using an intermediate model. - Masaki Kondo; Hidetoshi Onodera; Keikichi Tamaru (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998)

A Practical Gate Resizing Technique Considering Glitch Reduction for Low Power Design. - Masanori Hashimoto; Hidetoshi Onodera; Keikichi Tamaru (DAC, 1999)

A method for linking process-level variability to system performances. - Tomohiro Fujita; Ken-ichi Okada 001; Hiroaki Fujita; Hidetoshi Onodera; Keikichi Tamaru (ASP-DAC, 2000)