Physical random number generators for cryptographic application in mobile devices. - Shinichi Yasuda; Tetsufumi Tanamoto; Ryuji Ohba; Keiko Abe; Hanae Nozaki; Shinobu Fujita (ESSCIRC, 2005)

3D on-chip networking technology based on post-silicon devices for future networks-on-chip. - Shinobu Fujita; Kumiko Nomura; Keiko Abe; Thomas H. Lee (Nano-Net, 2006)

Novel Design of Three-Dimensional Crossbar for Future Network on Chip based on Post-Silicon Devices. - Kumiko Nomura; Keiko Abe; Shinobu Fujita; André DeHon (Nano-Net, 2006)

3-D Nanoarchitectures With Carbon Nanotube Mechanical Switches for Future On-Chip Network Beyond CMOS Architecture. - Shinobu Fujita; Kumiko Nomura; Keiko Abe; Thomas H. Lee (IEEE Trans. Circuits Syst. I Regul. Pap., 2007)

Perspectives and Issues in 3D-IC from Designers' Point of View. - Shinobu Fujita; Keiko Abe; Kumiko Nomura; Shinichi Yasuda; Tetsufumi Tanamoto (ISCAS, 2009)

High-performance FPGA based on novel DSS-MOSFET and non-volatile configuration memory (abstract only). - Shinichi Yasuda; Tetsufumi Tanamoto; Kazutaka Ikegami; Atsuhiro Kinoshita; Keiko Abe; Hirotaka Nishino; Shinobu Fujita (FPGA, 2010)

Performance analysis of 3D-IC for multi-core processors in sub-65nm CMOS technologies. - Kumiko Nomura; Keiko Abe; Shinobu Fujita; Yasuhiko Kurosawa; Atsushi Kageshima (ISCAS, 2010)

Designing Nonvolatile Reconfigurable Switch-based FPGA through Overall Circuit Performance Evaluation. - Kazutaka Ikegami; Keiko Abe; Kumiko Nomura; Shinichi Yasuda; Masato Oda; Shinobu Fujita (IPDPS Workshops, 2012)

D-MRAM cache: enhancing energy efficiency with 3T-1MTJ DRAM/MRAM hybrid memory. - Hiroki Noguchi; Kumiko Nomura; Keiko Abe; Shinobu Fujita; Eishi Arima; Kyundong Kim; Takashi Nakada; Shinobu Miwa; Hiroshi Nakamura (DATE, 2013)

Pictogram-based tablet application enabling patient input of emotions and behaviors. - Teruyoshi Hishiki; Hiroki Yasui; Yoshiko Matsunaga; Megumi Itoshima; Keiko Abe; Takahiko Norose; Takuro Tamura (AMIA, 2014)

Novel nonvolatile memory hierarchies to realize "normally-off mobile processors". - Shinobu Fujita; Kumiko Nomura; Hiroki Noguchi; Susumu Takeda; Keiko Abe (ASP-DAC, 2014)

Novel STT-MRAM-based last level caches for high performance processors using normally-off architectures. - Shinobu Fujita; Hiroki Noguchi; Kazutaka Ikegami; Susumu Takeda; Kumiko Nomura; Keiko Abe (ISIC, 2014)

7.5 A 3.3ns-access-time 71.2μW/MHz 1Mb embedded STT-MRAM using physically eliminated read-disturb scheme and normally-off memory architecture. - Hiroki Noguchi; Kazutaka Ikegami; Keiichi Kushida; Keiko Abe; Shogo Itai; Satoshi Takaya; Naoharu Shimomura; Junichi Ito; Atsushi Kawasumi; Hiroyuki Hara; Shinobu Fujita (ISSCC, 2015)

7.2 4Mb STT-MRAM-based cache with memory-access-aware power optimization and write-verify-write / read-modify-write scheme. - Hiroki Noguchi; Kazutaka Ikegami; Satoshi Takaya; Eishi Arima; Keiichi Kushida; Atsushi Kawasumi; Hiroyuki Hara; Keiko Abe; Naoharu Shimomura; Junichi Ito; Shinobu Fujita; Takashi Nakada; et al. (ISSCC, 2016)

Novel memory hierarchy with e-STT-MRAM for near-future applications. - Shinobu Fujita; Hiroki Noguchi; Kazutaka Ikegami; Susumu Takeda; Kumiko Nomura; Keiko Abe (VLSI-DAT, 2017)