The channeled-BSG: a universal floorplan for simultaneous place/route with IC applications. - Shigetoshi Nakatake; Keishi Sakanushi; Yoji Kajitani; Masahiro Kawakita (ICCAD, 1998)

The multi-BSG: stochastic approach to an optimum packing of convex-rectilinear blocks. - Keishi Sakanushi; Shigetoshi Nakatake; Yoji Kajitani (ICCAD, 1998)

An improved method of convex-shaped block packing based on sequence-pair [VLSI layout]. - Hiroaki Saito; Kazuya Wakata; Kunihiro Fujiyoshi; Keishi Sakanushi; Takayuki Obata (APCCAS (2), 2002)

An Enhanced Q-Sequence Augmented with Empty-Room-Insertion and Parenthesis Trees. - Changwen Zhuang; Yoji Kajitani; Keishi Sakanushi; Liyan Jin (DATE, 2002)

Recognition of Floorplan by Parametric BSG for Reuse of Layout Design. - Keishi Sakanushi; Zhonglin Wu; Yoji Kajitani (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002)

An extended representation of Q-sequence for optimizing channel-adjacency and routing-cost. - Changwen Zhuang; Keishi Sakanushi; Liyan Jin; Yoji Kajitani (ASP-DAC, 2003)

A Code Selection Method for SIMD Processors with PACK Instructions. - Hiroaki Tanaka; Shinsuke Kobayashi; Yoshinori Takeuchi; Keishi Sakanushi; Masaharu Imai (SCOPES, 2003)

An Improved Method of Convex Rectilinear Block Packing Based on Sequence-Pair. - Kazuya Wakata; Hiroaki Saito; Kunihiro Fujiyoshi; Keishi Sakanushi; Takayuki Obata; Chikaaki Kodama (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003)

Synthesizable HDL generation method for configurable VLIW processors. - Yuki Kobayashi; Shinsuke Kobayashi; Koji Okuda; Keishi Sakanushi; Yoshinori Takeuchi; Masaharu Imai (ASP-DAC, 2004)

Architecture-Level Performance Estimation for IP-Based Embedded Systems. - Kyoko Ueda; Keishi Sakanushi; Yoshinori Takeuchi; Masaharu Imai (DATE, 2004)

Towards a Higher Level of Abstraction in Hardware/Software Co-Simulation. - H. M. AbdElSalam; Shinsuke Kobayashi; Keishi Sakanushi; Yoshinori Takeuchi; Masaharu Imai (ICDCS Workshops, 2004)

S-sequence: a new floorplan representation method preserving room abutment relationships. - Yohei Ishimaru; Keishi Sakanushi; Shinsuke Kobayashi; Yoshinori Takeuchi; Masaharu Imai (ISCAS (4), 2004)

Enabling RTOS simulation modeling in a system level design language. - M. Abdelsalam Hassan; Keishi Sakanushi; Yoshinori Takeuchi; Masaharu Imai (ASP-DAC, 2005)

RTK-Spec TRON: A Simulation Model of an ITRON Based RTOS Kernel in SystemC. - M. Abdelsalam Hassan; Keishi Sakanushi; Yoshinori Takeuchi; Masaharu Imai (DATE, 2005)

Pack instruction generation for media pUsing multi-valued decision diagram. - Hiroaki Tanaka; Yoshinori Takeuchi; Keishi Sakanushi; Masaharu Imai; Yutaka Ota; Nobu Matsumoto; Masaki Nakagawa (CODES+ISSS, 2006)

Dynamic Reconfigurable Architecture Exploration based on Parameterized Reconfigurable Processor Model. - Ittetsu Taniguchi; Keishi Sakanushi; Kyoko Ueda; Yoshinori Takeuchi; Masaharu Imai (VLSI-SoC (Selected Papers), 2006)

Task Partitioning Oriented Architecture Exploration Method for Dynamic Reconfigurable Architectures. - Ittetsu Taniguchi; Kyoko Ueda; Keishi Sakanushi; Yoshinori Takeuchi; Masaharu Imai (VLSI-SoC, 2006)

A Processor Generation Method from Instruction Behavior Description Based on Specification of Pipeline Stages and Functional Units. - Takeshi Shiro; Masaaki Abe; Keishi Sakanushi; Yoshinori Takeuchi; Masaharu Imai (ASP-DAC, 2007)

A low power VLIW processor generation method by means of extracting non-redundant activation conditions. - Hirofumi Iwato; Keishi Sakanushi; Yoshinori Takeuchi; Masaharu Imai (CODES+ISSS, 2007)

A Block-Floating-Point Processor for Rapid Application Development. - Hiroaki Tanaka; Yoshinori Takeuchi; Keishi Sakanushi; Masaharu Imai; Shiro Kobayashi (ICASSP (2), 2007)

Generation of Pack Instruction Sequence for Media Processors Using Multi-Valued Decision Diagram. - Hiroaki Tanaka; Yoshinori Takeuchi; Keishi Sakanushi; Masaharu Imai; Hiroki Tagawa; Yutaka Ota; Nobu Matsumoto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007)

Systematic architecture exploration based on optimistic cycle estimation for low energy embedded processors. - Ittetsu Taniguchi; Murali Jayapala; Praveen Raghavan; Francky Catthoor; Keishi Sakanushi; Yoshinori Takeuchi; Masaharu Imai (ASP-DAC, 2009)

Heuristic Instruction Scheduling Algorithm Using Available Distance for Partial Forwarding Processor. - Takuji Hieda; Hiroaki Tanaka; Keishi Sakanushi; Yoshinori Takeuchi; Masaharu Imai (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

Optimal Scheme for Search State Space and Scheduling on Multiprocessor Systems. - Hassan A. Youness; Keishi Sakanushi; Yoshinori Takeuchi; Ashraf Salem; Abdel-Moniem Wahdan; Masaharu Imai (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

Two-stage configurable decoder model for multiple forward error correction standards. - Ittetsu Taniguchi; Ayataka Kobayashi; Keishi Sakanushi; Yoshinori Takeuchi; Masaharu Imai (ESTIMedia, 2010)

Efficient partitioning technique on multiple cores based on optimal scheduling and mapping algorithm. - Hassan A. Youness; Abdel-Moniem Wahdan; Mohammed Hassan; Ashraf Salem; Mohammed Moness; Keishi Sakanushi; Yoshinori Takeuchi; Masaharu Imai (ISCAS, 2010)

Advantage and Possibility of Application-domain Specific Instruction-set Processor (ASIP). - Masaharu Imai; Yoshinori Takeuchi; Keishi Sakanushi; Nagisa Ishiura (IPSJ Trans. Syst. LSI Des. Methodol., 2010)

A Low-power ASIP Generation Method by Extracting Minimum Execution Conditions. - Hirofumi Iwato; Keishi Sakanushi; Yoshinori Takeuchi; Masaharu Imai (IPSJ Trans. Syst. LSI Des. Methodol., 2010)

Electronic Triage System: Casualties Monitoring System in the Disaster Scene. - Keishi Sakanushi; Takuji Hieda; Taichiro Shiraishi; Yasumasa Ode; Yoshinori Takeuchi; Masaharu Imai; Teruo Higashino; Hiroshi Tanaka (3PGCIC, 2011)

Biological information sensing technologies for medical, health care, and wellness applications. - Masaharu Imai; Yoshinori Takeuchi; Keishi Sakanushi; Hirofumi Iwato (ASP-DAC, 2011)

Automated architecture exploration for low energy reconfigurable AGU. - Ittetsu Taniguchi; Murali Jayapala; Praveen Raghavan; Francky Catthoor; Keishi Sakanushi; Yoshinori Takeuchi; Masaharu Imai (ISOCC, 2011)

Two-Stage Configurable Decoder Model for Domain Specific FEC Decoder Design. - Ittetsu Taniguchi; Ayataka Kobayashi; Keishi Sakanushi; Yoshinori Takeuchi; Masaharu Imai (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011)

Task Allocation and Scheduling for Voltage-Frequency Islands Applied NoC-based MPSoC Considering Network Congestion. - Sho Ninomiya; Keishi Sakanushi; Yoshinori Takeuchi; Masaharu Imai (MCSoC, 2012)

On-chip Communication Buffer Architecture Optimization Considering Bus Width. - Salita Sombatsiri; Keishi Sakanushi; Yoshinori Takeuchi; Masaharu Imai (MCSoC, 2012)

A Small-Area and Low-Power SoC for Less-Invasive Pressure Sensing Capsules in Ambulatory Urodynamic Monitoring. - Hirofumi Iwato; Keishi Sakanushi; Yoshinori Takeuchi; Masaharu Imai (IEICE Trans. Electron., 2012)

Electronic triage system for continuously monitoring casualties at disaster scenes. - Keishi Sakanushi; Takuji Hieda; Taichiro Shiraishi; Yasumasa Ode; Yoshinori Takeuchi; Masaharu Imai; Teruo Higashino; Hiroshi Tanaka (J. Ambient Intell. Humaniz. Comput., 2013)