An ATMS-based geometric constraint solver for 3D CAD. - Shuichi Shimizu; Keisuke Inoue; Masayuki Numao (ICTAI, 1991)

ATTEMPT-1: A Reconfigurable Multiprocessor Testbed. - Keisuke Inoue; Toru Kisuki; Michitaka Okuno; Etsuko Shimizu; Takuya Terasawa; Hideharu Amano (FPL, 1996)

Shared vs. Snoop: Evaluation of Cache Structure for Single-Chip Multiprocessors. - Toru Kisuki; Masaki Wakabayashi; Junji Yamamoto; Keisuke Inoue; Hideharu Amano (Euro-Par, 1997)

Traffic Control Model with Neural Network Analogy. - Toru Ohira; Keisuke Inoue; Yoshiteru Takeshima (ICONIP (2), 1997)

A study on snoop cache systems for single-chip multiprocessors. - Takuya Terasawa; Keisuke Inoue; Hitoshi Kurosawa; Hideharu Amano (Syst. Comput. Jpn., 1997)

Automated Conversion of 2D Triangular Mesh into Quadrilateral Mesh with Directionality Control. - Takayuki Itoh; Kenji Shimada; Keisuke Inoue; Atsushi Yamada; Tomotake Furuhata (IMR, 1998)

ISIS: Multiprocessor Simulator Library. - Masaki Wakabayashi; Keisuke Inoue; Hideharu Amano (Applied Informatics, 1999)

Clustering Large Number of Faces for 2-Dimensional Mesh Generation. - Keisuke Inoue; Takayuki Itoh; Atsushi Yamada; Tomotake Furuhata; Kenji Shimada (IMR, 1999)

An Approach for Generating Meshes Similar to A Reference Mesh. - Atsushi Yamada; Keisuke Inoue; Takayuki Itoh; Kenji Shimada (IMR, 2000)

Face clustering of a large-scale CAD model for surface mesh generation. - Keisuke Inoue; Takayuki Itoh; Atsushi Yamada; Tomotake Furuhata; Kenji Shimada (Comput. Aided Des., 2001)

A 250-MHz single-chip multiprocessor for audio and video signal processing. - Tatsuya Koyama; Keisuke Inoue; Hirokazu Hanaki; Masahiro Yasue; Eiji Iwata (IEEE J. Solid State Circuits, 2001)

A Novel Robot Vision Applicable to Real-time Target Tracking. - Kazuhiro Shimonomura; Keisuke Inoue; Seiji Kameda; Tetsuya Yagi (J. Robotics Mechatronics, 2003)

Knowledge Discovery from Heterogeneous Dynamic Systems using Change-Point Correlations. - Tsuyoshi Idé; Keisuke Inoue (SDM, 2005)

Social dynamics of free and open source team communications. - James Howison; Keisuke Inoue; Kevin Crowston (OSS, 2006)

Safe clocking register assignment in datapath synthesis. - Keisuke Inoue; Mineo Kaneko; Tsuyoshi Iwagaki (ICCD, 2008)

Novel Register Sharing in Datapath for Structural Robustness against Delay Variation. - Keisuke Inoue; Mineo Kaneko; Tsuyoshi Iwagaki (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)

Discourse analysis of online chat reference interviews for modeling online information-seeking dialogues. - Keisuke Inoue (ASIST, 2009)

Safe clocking for the setup and hold timing constraints in datapath synthesis. - Keisuke Inoue; Mineo Kaneko; Tsuyoshi Iwagaki (ACM Great Lakes Symposium on VLSI, 2009)

Optimal Register Assignment with Minimum-Path Delay Compensation for Variation-Aware Datapaths. - Keisuke Inoue; Mineo Kaneko; Tsuyoshi Iwagaki (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

Optimal register assignment with minimum-delay compensation for latch-based design. - Keisuke Inoue; Mineo Kaneko (APCCAS, 2010)

A novel resource sharing model and high-level synthesis for delay variability-tolerant datapaths. - Keisuke Inoue; Mineo Kaneko (ACM Great Lakes Symposium on VLSI, 2010)

Ordered coloring-based resource binding for datapaths with improved skew-adjustability. - Mineo Kaneko; Keisuke Inoue (ACM Great Lakes Symposium on VLSI, 2011)

Variable-duty-cycle scheduling in double-edge-triggered flip-flop-based high-level synthesis. - Keisuke Inoue; Mineo Kaneko (ISCAS, 2011)

Early planning for RT-level delay insertion during clock skew-aware register binding. - Keisuke Inoue; Mineo Kaneko (VLSI-SoC, 2011)

Backward-Data-Direction Clocking and Relevant Optimal Register Assignment in Datapath Synthesis. - Keisuke Inoue; Mineo Kaneko; Tsuyoshi Iwagaki (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011)

Framework for Latch-based High-level Synthesis Using Minimum-delay Compensation. - Keisuke Inoue; Mineo Kaneko (IPSJ Trans. Syst. LSI Des. Methodol., 2011)

Performance-driven register write inhibition in high-level synthesis under strict maximum-permissible clock latency range. - Keisuke Inoue; Mineo Kaneko (ASP-DAC, 2012)

Optimal register-type selection during resource binding in flip-flop/latch-based high-level synthesis. - Keisuke Inoue; Mineo Kaneko (ACM Great Lakes Symposium on VLSI, 2012)

Reliable and low-power clock distribution using pre- and post-silicon delay adaptation in high-level synthesis. - Keisuke Inoue; Mineo Kaneko (ISCAS, 2012)

Register binding and domain assignment for multi-domain clock skew scheduling-aware high-level synthesis. - Keisuke Inoue; Mineo Kaneko (ISQED, 2012)

Statistical timing-yield driven scheduling and FU binding in latch-based datapath synthesis. - Keisuke Inoue; Mineo Kaneko (MWSCAS, 2012)

A Formal Approach to Optimal Register Binding with Ordered Clocking for Clock-Skew Tolerant Datapaths. - Keisuke Inoue; Mineo Kaneko (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012)

Heuristic and Exact Resource Binding Algorithms for Storage Optimization Using Flip-Flops and Latches. - Keisuke Inoue; Mineo Kaneko (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013)

Dual-Edge-Triggered Flip-Flop-Based High-Level Synthesis with Programmable Duty Cycle. - Keisuke Inoue; Mineo Kaneko (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013)

Spanning Distribution Forests of Graphs - (Extended Abstract). - Keisuke Inoue; Takao Nishizeki (FAW, 2014)

An ILP-Based Optimal Circuit Mapping Method for PLDs. - Hiroki Nishiyama 003; Masato Inagi; Shin'ichi Wakabayashi; Shinobu Nagayama; Keisuke Inoue; Mineo Kaneko (IPDPS Workshops, 2014)

Bitwidth-aware register allocation and binding for clock period minimization. - Keisuke Inoue; Mineo Kaneko (MWSCAS, 2015)

ECC module optimization for storage transient error-tolerant ASICs. - Keisuke Inoue (ICECS, 2016)

A dependable ASIC architecture with RT-level rollback for controller soft error recovery. - Keisuke Inoue (NORCAS, 2017)

Automatic Examination-Based Whitelist Generation for XSS Attack Detection. - Keisuke Inoue; Toshiki Honda; Kohei Mukaiyama; Tetsushi Ohki; Masakatsu Nishigaki (BWCCA, 2018)

An ILP-based Optimization Method for Radiation Hardened Register and ECC Mixed Architectures. - Keisuke Inoue (VLSI-SoC, 2019)

Removing Reflection from In-vehicle Camera Image. - Keisuke Inoue; Fumihiko Sakaue; Jun Sato (VISIGRAPP (4: VISAPP), 2020)

Study on Vibration Characteristics of Bolted and Bonded Joints by Using Acceleration Sensors. - Shogo Isobe; Tristan Samuel Britton Fujimori; Yoshinao Kishimoto; Yukiyoshi Kobayashi; Keisuke Inoue (IEEE SENSORS, 2024)

Establishing Utilization Decision Criteria for Open-Source Software Projects Based on Issue Resolution Time Evaluation. - Keisuke Inoue; Kazuhiko Tsuda (ICSTW, 2025)