Hybrid quick error detection (H-QED): accelerator validation and debug using high-level synthesis principles. - Keith A. Campbell; David Lin; Subhasish Mitra; Deming Chen (DAC, 2015)

High-level synthesis of error detecting cores through low-cost modulo-3 shadow datapaths. - Keith A. Campbell; Pranay Vissa; David Z. Pan; Deming Chen (DAC, 2015)

High-level Synthesis for Low-power Design. - Zhiru Zhang; Deming Chen; Steve Dai; Keith A. Campbell (IPSJ Trans. Syst. LSI Des. Methodol., 2015)

Designing high-quality hardware on a development effort budget: A study of the current state of high-level synthesis. - Zelei Sun; Keith A. Campbell; Wei Zuo; Kyle Rupnow; Swathi T. Gurumani; Frederic Doucet; Deming Chen (ASP-DAC, 2016)

Debugging and verifying SoC designs through effective cross-layer hardware-software co-simulation. - Keith A. Campbell; Leon He; Liwei Yang; Swathi T. Gurumani; Kyle Rupnow; Deming Chen (DAC, 2016)

Cross-Layer Resilience in Low-Voltage Digital Systems: Key Insights. - Eric Cheng; Jacob A. Abraham; Pradip Bose; Alper Buyuktosunoglu; Keith A. Campbell; Deming Chen; Chen-Yong Cher; Hyungmin Cho; Binh Q. Le; Klas Lilja; Shahrzad Mirkhani; Kevin Skadron; et al. (ICCD, 2017)

New advances of high-level synthesis for efficient and reliable hardware design. - Keith A. Campbell; Wei Zuo; Deming Chen (Integr., 2017)

Robust and reliable hardware accelerator design through high-level synthesis - Keith A. Campbell (2017)

Low-cost hardware architectures for mersenne modulo functional units. - Keith A. Campbell; Chen-Hsuan Lin 001; Deming Chen (ASP-DAC, 2018)

Cost-Effective Error Detection Through Mersenne Modulo Shadow Datapaths. - Keith A. Campbell; Chen-Hsuan Lin 001; Deming Chen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

Hybrid Quick Error Detection: Validation and Debug of SoCs Through High-Level Synthesis. - Keith A. Campbell; David Lin; Leon He; Liwei Yang; Swathi T. Gurumani; Kyle Rupnow; Subhasish Mitra; Deming Chen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)