Bit-Interleaving-Enabled 8T SRAM With Shared Data-Aware Write and Reference-Based Sense Amplifier. - Liang Wen; Xu Cheng 002; Keji Zhou; Shudong Tian; Xiaoyang Zeng (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

Nonvolatile Crossbar 2D2R TCAM with Cell Size of 16.3 F2 and K-means Clustering for Power Reduction. - Keji Zhou; Xiaoyong Xue; Jianguo Yang; Xiaoxin Xu; Hangbing Lv; Mingyu Wang 001; Ming-e Jing; Wenjun Liu; Xiaoyang Zeng; Steve S. Chung; Jing Li; Ming Liu 022 (A-SSCC, 2018)

Nonvolatile Binary CNN Accelerator with Extremely Low Standby Power using RRAM for IoT Applications. - Yujie Cai; Keji Zhou; Xiaoyong Xue; Mingyu Wang; Xiaoyang Zeng (ASICON, 2019)

Toward Practical Digital Phase Alignment for Coherent Beam Combining in Multi-Aperture Free Space Coherent Optical Receivers. - Chenjie Rao; Sheng Cui; Yicong Tu; Keji Zhou; Deming Liu (IEEE Access, 2020)

High-Density 3-D Stackable Crossbar 2D2R nvTCAM With Low-Power Intelligent Search for Fast Packet Forwarding in 5G Applications. - Keji Zhou; Xiaoyong Xue; Jianguo Yang; Xiaoxin Xu; Hangbing Lv; Ming-e Jing; Jing Li; Xiaoyang Zeng; Ming Liu 022 (IEEE J. Solid State Circuits, 2021)

An Energy Efficient Computing-in-Memory Accelerator With 1T2R Cell and Fully Analog Processing for Edge AI Applications. - Keji Zhou; Chenyang Zhao 008; Jinbei Fang; Jingwen Jiang; Deyang Chen; Yujie Huang; Ming-e Jing; Jun Han 003; Haidong Tian; Xiankui Xiong; Qi Liu 010; Xiaoyong Xue; et al. (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

A 200M-Query-Vector/s Computing-in-RRAM ADC-less k-Nearest-Neighbor Accelerator with Time-Domain Winner-Takes-All Circuits. - Chen Mu; Yunzhengmao Wang; Jiapei Zheng; Shiwei Liu 002; Keji Zhou; Shan Tang; Chixiao Chen; Qi Liu 010 (AICAS, 2022)

Toward Practical Temporal Diversity Coherent Combining Based Variable Data-Rate Free Space Optical Communication Systems. - Faming Li; Sheng Cui; Yanan Chen; Chenjie Rao; Yicong Tu; Keji Zhou; Deming Liu (IEEE Access, 2022)

A 28 nm 81 Kb 59-95.3 TOPS/W 4T2R ReRAM Computing-in-Memory Accelerator With Voltage-to-Time-to-Digital Based Output. - Keji Zhou; Xinru Jia; Chenyang Zhao 008; Xumeng Zhang; Guangjian Wu; Chen Mu; Haozhe Zhu; Yanting Ding; Chixiao Chen; Xiaoyong Xue; Xiaoyang Zeng; Qi Liu 010 (IEEE J. Emerg. Sel. Topics Circuits Syst., 2022)

A 28 nm 512 Kb adjacent 2T2R RRAM PUF with interleaved cell mirroring and self-adaptive splitting for high density and low BER cryptographic key in IoT devices. - Jianguo Yang; Ruijun Lin; Keji Zhou; Yuejun Zhang; Xiaoyong Xue; Hangbing Lv (Microelectron. J., 2022)

A 2D2R ReRAM CIM accelerator for multilayer perceptron in visual classification applications. - Keji Zhou; Ruijun Lin; Zhiwang Guo; Yixuan Liu; Jingwen Jiang; Chenyang Zhao; Jinbei Fang; Xiaoxin Xu; Xiaoyong Xue; Xiaoyang Zeng (Microelectron. J., 2022)

A 1T2R1C ReRAM CIM Accelerator With Energy-Efficient Voltage Division and Capacitive Coupling for CNN Acceleration in AI Edge Applications. - Deyang Chen; Zhiwang Guo; Jinbei Fang; Chenyang Zhao 008; Jingwen Jiang; Keji Zhou; Haidong Tian; Xiankui Xiong; Xiaoyong Xue; Xiaoyang Zeng (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

An Emerging NVM CIM Accelerator With Shared-Path Transpose Read and Bit-Interleaving Weight Storage for Efficient On-Chip Training in Edge Devices. - Zhiwang Guo; Deyang Chen; Chenyang Zhao 008; Jinbei Fang; Jingwen Jiang; Yixuan Liu; Haidong Tian; Xiankui Xiong; Keji Zhou; Xiaoyong Xue; Qi Liu 010; Xiaoyang Zeng (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

Multicore Spiking Neuromorphic Chip in 180-nm With ReRAM Synapses and Digital Neurons. - Hao Jiang 024; Jikai Lu; Chenggao Zhang; Shuangzhu Tang; Junjie An; Lingli Cheng; Jian Lu; Jinsong Wei; Keji Zhou; Xumeng Zhang; Tuo Shi; Qi Liu 010 (IEEE J. Emerg. Sel. Topics Circuits Syst., 2023)

Tempo-CIM: A RRAM Compute-in-Memory Neuromorphic Accelerator With Area-Efficient LIF Neuron and Split-Train-Merged-Inference Algorithm for Edge AI Applications. - Jingwen Jiang; Keji Zhou; Jinhao Liang; Fengshi Tian; Chenyang Zhao 008; Jianguo Yang; Xiaoyong Xue; Xiaoyang Zeng (IEEE J. Emerg. Sel. Topics Circuits Syst., 2023)

HARDSEA: Hybrid Analog-ReRAM Clustering and Digital-SRAM In-Memory Computing Accelerator for Dynamic Sparse Self-Attention in Transformer. - Shiwei Liu 002; Chen Mu; Hao Jiang 024; Yunzhengmao Wang; Jinshan Zhang 006; Feng Lin; Keji Zhou; Qi Liu 010; Chixiao Chen (IEEE Trans. Very Large Scale Integr. Syst., 2024)

A Scalable Area-Efficient Low-Delay Asynchronous AER Circuits Design for Neuromorphic Chips. - Siyuan Ouyang; Keji Zhou; Hao Jiang 024; Chenyang Li; Jinhao Liang; Fangduo Zhu; Xumeng Zhang; Qi Liu 010 (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

SRIF: Energy- and Area-Efficient Soft Reset Integrate-and-Fire Neuron for High-Accuracy Spiking Neural Network. - Tianci Cai; Qiqiao Wu; Yixuan Liu; Yue Cao; Yu Jiang; Keji Zhou; Jianguo Yang (ISCAS, 2025)

A Refresh-Reduction Digital eDRAM CIM Macro using Asymmetric Error Tolerance Scheme. - Yue Cao; Yuanyuan Han; Keji Zhou; Chengshuo Yu; Tianci Cai; Jianguo Yang (ISCAS, 2025)

A High-Density RRAM-Based Ising Machine with Analog In-Memory Operation for Solving Combinatorial Optimization Problems. - Jingxin Deng; Keji Zhou; Honghu Yang; Chengshuo Yu; Jianguo Yang (ISCAS, 2025)

A High Performance Dual-Wordline RRAM Macro with Replica Bitline Delay Control Circuit. - Honghu Yang; Yongkang Han; Tianci Cai; Chengshuo Yu; Keji Zhou; Jianguo Yang (ISCAS, 2025)

A Novel Neuromorphic Hardware Using Area-Efficient Chain RRAM-Based Synapses and Compact Neurons With (Anti-) Integration Scheme. - Qiqiao Wu; Honghu Yang; Yixuan Liu; Yue Cao; Yongkang Han; Haijun Jiang; Keji Zhou; Hailan Yi; Jianguo Yang; Qi Liu 010 (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

Enhancing All-to-All RRAM Ising Machines With Randomized Granular Update Strategies for Solving Combinatorial Optimization Problems. - Yixuan Liu; Qiqiao Wu; Honghu Yang; Chengshuo Yu; Keji Zhou; Yu Jiang; Haijun Jiang; Hailan Yi; Xiaoyong Xue; Jianguo Yang; Xiaoyang Zeng (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)