An Automatic Post Silicon Clock Tuning System for Improving System Performance based on Tester Measurements. - Kelageri Nagaraj; Sandip Kundu (ITC, 2008)

A study on placement of post silicon clock tuning buffers for mitigating impact of process variation. - Kelageri Nagaraj; Sandip Kundu (DATE, 2009)

Process variation mitigation via post silicon clock tuning. - Kelageri Nagaraj; Sandip Kundu (ACM Great Lakes Symposium on VLSI, 2009)