A Compact Model for Analysis and Design of On-chip Power Network with Decoupling Capacitors. - Payman Zarkesh-Ha; Ken Doniger; William Loh; Dechang Sun; Rick Stephani; Gordon Priebe (ICCD, 2003)

Impact of Interconnect Pattern Density Information on a 90nm Technology ASIC Design Flow. - Payman Zarkesh-Ha; S. Lakshminarayann; Ken Doniger; William Loh; Peter Wright (ISQED, 2003)

Prediction of interconnect pattern density distribution: derivation, validation, and applications. - Payman Zarkesh-Ha; Ken Doniger; William Loh; Peter Wright (SLIP, 2003)

Prediction of interconnect adjacency distribution: derivation, validation, and applications. - Payman Zarkesh-Ha; Ken Doniger; William Loh; Peter Bendix (SLIP, 2004)

Stochastic interconnect layout sensitivity model. - Payman Zarkesh-Ha; Ken Doniger (SLIP, 2007)