Clock design of 300MHz 128-bit 2-way superscalar microprocessor. - Fujio Ishihara; Christian Klinger; Ken-ichi Agawa (ASP-DAC, 2000)

A bitline leakage compensation scheme for low-voltage SRAMs. - Ken-ichi Agawa; Hiroyuki Hara; Toshinari Takayanagi; Tadahiro Kuroda (IEEE J. Solid State Circuits, 2001)