32 x 32 Shared Buffer Type ATM Switch VLSI's for B-ISDN's. - Takahiko Kozaki; Noboru Endo; Yoshito Sakurai; Osamu Matsubara; Masao Mizukami; Ken'ichi Asano (IEEE J. Sel. Areas Commun., 1991)

A single-chip MPEG2 422@ML video, audio, and system encoder with a 162-MHz media-processor and dual motion estimation cores. - Satoshi Kumaki; Tetsuya Matsumura; Kamya Ishihara; Hiroshi Segawa; Kiyofumi Kawamoto; Hideo Ohira; Toshiaki Shimada; Hidenori Sato; Takashi Hattori; Tetsuro Wada; Hiroshi Honma; Tetsuya Watanabe; et al. (CICC, 1999)

Media processor core architecture for realtime, bi-directional MPEG4/H.26X codec with 30 fr/s for CIF-video. - T. Kamemaru; Hideo Ohira; H. Suzuki; Ken'ichi Asano; Masahiko Yoshimoto; Tokumichi Murakami (CICC, 2000)