Fuzzy inference and fuzzy inference processor. - Kazuo Nakamura; Narumi Sakashita; Yasuhiko Nitta; Ken'ichi Shimomura; Takeshi Tokuda (IEEE Micro, 1993)

A Built-In Self-Test Circuit with Timing Margin Test Function in a 1Gbit Synchronous DRAM. - Narumi Sakashita; Fumihiro Okuda; Ken'ichi Shimomura; Hiroki Shimano; Mitsuhiro Hamada; Tetsuo Tada; Shinji Komori; Kazuo Kyuma; Akihiko Yasuoka; Haruhiko Abe (ITC, 1996)

A 1.6-GB/s data-rate 1-Gb synchronous DRAM with hierarchical square-shaped memory block and distributed bank architecture. - Narumi Sakashita; Yasuhiko Nitta; Ken'ichi Shimomura; Fumihiro Okuda; Hiroki Shimano; Satoshi Yamakawa; Masaki Tsukude; Kazutami Arimoto; Shinji Baba; Shinji Komori; Kazuo Kyuma; Akihiko Yasuoka; et al. (IEEE J. Solid State Circuits, 1996)

A 1-V 46-ns 16-Mb SOI-DRAM with body control technique. - Ken'ichi Shimomura; Hiroki Shimano; Narumi Sakashita; Fumihiro Okuda; Toshiyuki Oashi; Yasuo Yamaguchi; Takahisa Eimori; Masahide Inuishi; Kazutami Arimoto; Shigeto Maegawa; Yasuo Inoue; Shinji Komori; et al. (IEEE J. Solid State Circuits, 1997)